// soc_system_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 14.1 186 at 2015.01.07.15:40:04

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
		input  wire [11:0] hps_0_h2f_axi_master_awid,                                        //                                       hps_0_h2f_axi_master.awid
		input  wire [29:0] hps_0_h2f_axi_master_awaddr,                                      //                                                           .awaddr
		input  wire [3:0]  hps_0_h2f_axi_master_awlen,                                       //                                                           .awlen
		input  wire [2:0]  hps_0_h2f_axi_master_awsize,                                      //                                                           .awsize
		input  wire [1:0]  hps_0_h2f_axi_master_awburst,                                     //                                                           .awburst
		input  wire [1:0]  hps_0_h2f_axi_master_awlock,                                      //                                                           .awlock
		input  wire [3:0]  hps_0_h2f_axi_master_awcache,                                     //                                                           .awcache
		input  wire [2:0]  hps_0_h2f_axi_master_awprot,                                      //                                                           .awprot
		input  wire        hps_0_h2f_axi_master_awvalid,                                     //                                                           .awvalid
		output wire        hps_0_h2f_axi_master_awready,                                     //                                                           .awready
		input  wire [11:0] hps_0_h2f_axi_master_wid,                                         //                                                           .wid
		input  wire [63:0] hps_0_h2f_axi_master_wdata,                                       //                                                           .wdata
		input  wire [7:0]  hps_0_h2f_axi_master_wstrb,                                       //                                                           .wstrb
		input  wire        hps_0_h2f_axi_master_wlast,                                       //                                                           .wlast
		input  wire        hps_0_h2f_axi_master_wvalid,                                      //                                                           .wvalid
		output wire        hps_0_h2f_axi_master_wready,                                      //                                                           .wready
		output wire [11:0] hps_0_h2f_axi_master_bid,                                         //                                                           .bid
		output wire [1:0]  hps_0_h2f_axi_master_bresp,                                       //                                                           .bresp
		output wire        hps_0_h2f_axi_master_bvalid,                                      //                                                           .bvalid
		input  wire        hps_0_h2f_axi_master_bready,                                      //                                                           .bready
		input  wire [11:0] hps_0_h2f_axi_master_arid,                                        //                                                           .arid
		input  wire [29:0] hps_0_h2f_axi_master_araddr,                                      //                                                           .araddr
		input  wire [3:0]  hps_0_h2f_axi_master_arlen,                                       //                                                           .arlen
		input  wire [2:0]  hps_0_h2f_axi_master_arsize,                                      //                                                           .arsize
		input  wire [1:0]  hps_0_h2f_axi_master_arburst,                                     //                                                           .arburst
		input  wire [1:0]  hps_0_h2f_axi_master_arlock,                                      //                                                           .arlock
		input  wire [3:0]  hps_0_h2f_axi_master_arcache,                                     //                                                           .arcache
		input  wire [2:0]  hps_0_h2f_axi_master_arprot,                                      //                                                           .arprot
		input  wire        hps_0_h2f_axi_master_arvalid,                                     //                                                           .arvalid
		output wire        hps_0_h2f_axi_master_arready,                                     //                                                           .arready
		output wire [11:0] hps_0_h2f_axi_master_rid,                                         //                                                           .rid
		output wire [63:0] hps_0_h2f_axi_master_rdata,                                       //                                                           .rdata
		output wire [1:0]  hps_0_h2f_axi_master_rresp,                                       //                                                           .rresp
		output wire        hps_0_h2f_axi_master_rlast,                                       //                                                           .rlast
		output wire        hps_0_h2f_axi_master_rvalid,                                      //                                                           .rvalid
		input  wire        hps_0_h2f_axi_master_rready,                                      //                                                           .rready
		input  wire [11:0] hps_0_h2f_lw_axi_master_awid,                                     //                                    hps_0_h2f_lw_axi_master.awid
		input  wire [20:0] hps_0_h2f_lw_axi_master_awaddr,                                   //                                                           .awaddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awlen,                                    //                                                           .awlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awsize,                                   //                                                           .awsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awburst,                                  //                                                           .awburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awlock,                                   //                                                           .awlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awcache,                                  //                                                           .awcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awprot,                                   //                                                           .awprot
		input  wire        hps_0_h2f_lw_axi_master_awvalid,                                  //                                                           .awvalid
		output wire        hps_0_h2f_lw_axi_master_awready,                                  //                                                           .awready
		input  wire [11:0] hps_0_h2f_lw_axi_master_wid,                                      //                                                           .wid
		input  wire [31:0] hps_0_h2f_lw_axi_master_wdata,                                    //                                                           .wdata
		input  wire [3:0]  hps_0_h2f_lw_axi_master_wstrb,                                    //                                                           .wstrb
		input  wire        hps_0_h2f_lw_axi_master_wlast,                                    //                                                           .wlast
		input  wire        hps_0_h2f_lw_axi_master_wvalid,                                   //                                                           .wvalid
		output wire        hps_0_h2f_lw_axi_master_wready,                                   //                                                           .wready
		output wire [11:0] hps_0_h2f_lw_axi_master_bid,                                      //                                                           .bid
		output wire [1:0]  hps_0_h2f_lw_axi_master_bresp,                                    //                                                           .bresp
		output wire        hps_0_h2f_lw_axi_master_bvalid,                                   //                                                           .bvalid
		input  wire        hps_0_h2f_lw_axi_master_bready,                                   //                                                           .bready
		input  wire [11:0] hps_0_h2f_lw_axi_master_arid,                                     //                                                           .arid
		input  wire [20:0] hps_0_h2f_lw_axi_master_araddr,                                   //                                                           .araddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arlen,                                    //                                                           .arlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arsize,                                   //                                                           .arsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arburst,                                  //                                                           .arburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arlock,                                   //                                                           .arlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arcache,                                  //                                                           .arcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arprot,                                   //                                                           .arprot
		input  wire        hps_0_h2f_lw_axi_master_arvalid,                                  //                                                           .arvalid
		output wire        hps_0_h2f_lw_axi_master_arready,                                  //                                                           .arready
		output wire [11:0] hps_0_h2f_lw_axi_master_rid,                                      //                                                           .rid
		output wire [31:0] hps_0_h2f_lw_axi_master_rdata,                                    //                                                           .rdata
		output wire [1:0]  hps_0_h2f_lw_axi_master_rresp,                                    //                                                           .rresp
		output wire        hps_0_h2f_lw_axi_master_rlast,                                    //                                                           .rlast
		output wire        hps_0_h2f_lw_axi_master_rvalid,                                   //                                                           .rvalid
		input  wire        hps_0_h2f_lw_axi_master_rready,                                   //                                                           .rready
		input  wire        clk_0_clk_clk,                                                    //                                                  clk_0_clk.clk
		input  wire        fpga_only_master_clk_reset_reset_bridge_in_reset_reset,           //           fpga_only_master_clk_reset_reset_bridge_in_reset.reset
		input  wire        hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		input  wire        onchip_memory2_0_reset1_reset_bridge_in_reset_reset,              //              onchip_memory2_0_reset1_reset_bridge_in_reset.reset
		input  wire [31:0] fpga_only_master_master_address,                                  //                                    fpga_only_master_master.address
		output wire        fpga_only_master_master_waitrequest,                              //                                                           .waitrequest
		input  wire [3:0]  fpga_only_master_master_byteenable,                               //                                                           .byteenable
		input  wire        fpga_only_master_master_read,                                     //                                                           .read
		output wire [31:0] fpga_only_master_master_readdata,                                 //                                                           .readdata
		output wire        fpga_only_master_master_readdatavalid,                            //                                                           .readdatavalid
		input  wire        fpga_only_master_master_write,                                    //                                                           .write
		input  wire [31:0] fpga_only_master_master_writedata,                                //                                                           .writedata
		output wire [0:0]  intr_capturer_0_avalon_slave_0_address,                           //                             intr_capturer_0_avalon_slave_0.address
		output wire        intr_capturer_0_avalon_slave_0_read,                              //                                                           .read
		input  wire [31:0] intr_capturer_0_avalon_slave_0_readdata,                          //                                                           .readdata
		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,                              //                                jtag_uart_avalon_jtag_slave.address
		output wire        jtag_uart_avalon_jtag_slave_write,                                //                                                           .write
		output wire        jtag_uart_avalon_jtag_slave_read,                                 //                                                           .read
		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,                             //                                                           .readdata
		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,                            //                                                           .writedata
		input  wire        jtag_uart_avalon_jtag_slave_waitrequest,                          //                                                           .waitrequest
		output wire        jtag_uart_avalon_jtag_slave_chipselect,                           //                                                           .chipselect
		output wire [12:0] onchip_memory2_0_s1_address,                                      //                                        onchip_memory2_0_s1.address
		output wire        onchip_memory2_0_s1_write,                                        //                                                           .write
		input  wire [63:0] onchip_memory2_0_s1_readdata,                                     //                                                           .readdata
		output wire [63:0] onchip_memory2_0_s1_writedata,                                    //                                                           .writedata
		output wire [7:0]  onchip_memory2_0_s1_byteenable,                                   //                                                           .byteenable
		output wire        onchip_memory2_0_s1_chipselect,                                   //                                                           .chipselect
		output wire        onchip_memory2_0_s1_clken,                                        //                                                           .clken
		output wire [0:0]  sysid_qsys_control_slave_address,                                 //                                   sysid_qsys_control_slave.address
		input  wire [31:0] sysid_qsys_control_slave_readdata                                 //                                                           .readdata
	);

	wire          rsp_mux_src_valid;                                                                  // rsp_mux:src_valid -> hps_0_h2f_axi_master_agent:write_rp_valid
	wire  [162:0] rsp_mux_src_data;                                                                   // rsp_mux:src_data -> hps_0_h2f_axi_master_agent:write_rp_data
	wire          rsp_mux_src_ready;                                                                  // hps_0_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
	wire    [4:0] rsp_mux_src_channel;                                                                // rsp_mux:src_channel -> hps_0_h2f_axi_master_agent:write_rp_channel
	wire          rsp_mux_src_startofpacket;                                                          // rsp_mux:src_startofpacket -> hps_0_h2f_axi_master_agent:write_rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                            // rsp_mux:src_endofpacket -> hps_0_h2f_axi_master_agent:write_rp_endofpacket
	wire          rsp_mux_001_src_valid;                                                              // rsp_mux_001:src_valid -> hps_0_h2f_axi_master_agent:read_rp_valid
	wire  [162:0] rsp_mux_001_src_data;                                                               // rsp_mux_001:src_data -> hps_0_h2f_axi_master_agent:read_rp_data
	wire          rsp_mux_001_src_ready;                                                              // hps_0_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
	wire    [4:0] rsp_mux_001_src_channel;                                                            // rsp_mux_001:src_channel -> hps_0_h2f_axi_master_agent:read_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                                      // rsp_mux_001:src_startofpacket -> hps_0_h2f_axi_master_agent:read_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                        // rsp_mux_001:src_endofpacket -> hps_0_h2f_axi_master_agent:read_rp_endofpacket
	wire          fpga_only_master_master_translator_avalon_universal_master_0_waitrequest;           // fpga_only_master_master_agent:av_waitrequest -> fpga_only_master_master_translator:uav_waitrequest
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_readdata;              // fpga_only_master_master_agent:av_readdata -> fpga_only_master_master_translator:uav_readdata
	wire          fpga_only_master_master_translator_avalon_universal_master_0_debugaccess;           // fpga_only_master_master_translator:uav_debugaccess -> fpga_only_master_master_agent:av_debugaccess
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_address;               // fpga_only_master_master_translator:uav_address -> fpga_only_master_master_agent:av_address
	wire          fpga_only_master_master_translator_avalon_universal_master_0_read;                  // fpga_only_master_master_translator:uav_read -> fpga_only_master_master_agent:av_read
	wire    [3:0] fpga_only_master_master_translator_avalon_universal_master_0_byteenable;            // fpga_only_master_master_translator:uav_byteenable -> fpga_only_master_master_agent:av_byteenable
	wire          fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid;         // fpga_only_master_master_agent:av_readdatavalid -> fpga_only_master_master_translator:uav_readdatavalid
	wire          fpga_only_master_master_translator_avalon_universal_master_0_lock;                  // fpga_only_master_master_translator:uav_lock -> fpga_only_master_master_agent:av_lock
	wire          fpga_only_master_master_translator_avalon_universal_master_0_write;                 // fpga_only_master_master_translator:uav_write -> fpga_only_master_master_agent:av_write
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_writedata;             // fpga_only_master_master_translator:uav_writedata -> fpga_only_master_master_agent:av_writedata
	wire    [2:0] fpga_only_master_master_translator_avalon_universal_master_0_burstcount;            // fpga_only_master_master_translator:uav_burstcount -> fpga_only_master_master_agent:av_burstcount
	wire   [63:0] onchip_memory2_0_s1_agent_m0_readdata;                                              // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
	wire          onchip_memory2_0_s1_agent_m0_waitrequest;                                           // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
	wire          onchip_memory2_0_s1_agent_m0_debugaccess;                                           // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
	wire   [31:0] onchip_memory2_0_s1_agent_m0_address;                                               // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
	wire    [7:0] onchip_memory2_0_s1_agent_m0_byteenable;                                            // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
	wire          onchip_memory2_0_s1_agent_m0_read;                                                  // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
	wire          onchip_memory2_0_s1_agent_m0_readdatavalid;                                         // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
	wire          onchip_memory2_0_s1_agent_m0_lock;                                                  // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
	wire   [63:0] onchip_memory2_0_s1_agent_m0_writedata;                                             // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
	wire          onchip_memory2_0_s1_agent_m0_write;                                                 // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
	wire    [3:0] onchip_memory2_0_s1_agent_m0_burstcount;                                            // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
	wire          onchip_memory2_0_s1_agent_rf_source_valid;                                          // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
	wire  [163:0] onchip_memory2_0_s1_agent_rf_source_data;                                           // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
	wire          onchip_memory2_0_s1_agent_rf_source_ready;                                          // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
	wire          onchip_memory2_0_s1_agent_rf_source_startofpacket;                                  // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
	wire          onchip_memory2_0_s1_agent_rf_source_endofpacket;                                    // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_valid;                                       // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
	wire  [163:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data;                                        // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_ready;                                       // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket;                               // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket;                                 // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
	wire          onchip_memory2_0_s1_agent_rdata_fifo_src_valid;                                     // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent_rdata_fifo:in_valid
	wire   [65:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data;                                      // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent_rdata_fifo:in_data
	wire          onchip_memory2_0_s1_agent_rdata_fifo_src_ready;                                     // onchip_memory2_0_s1_agent_rdata_fifo:in_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
	wire          onchip_memory2_0_s1_agent_rdata_fifo_out_valid;                                     // onchip_memory2_0_s1_agent_rdata_fifo:out_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
	wire   [65:0] onchip_memory2_0_s1_agent_rdata_fifo_out_data;                                      // onchip_memory2_0_s1_agent_rdata_fifo:out_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
	wire          onchip_memory2_0_s1_agent_rdata_fifo_out_ready;                                     // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_agent_rdata_fifo:out_ready
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                                      // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                                   // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
	wire          jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                                   // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                                       // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire    [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                                    // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire          jtag_uart_avalon_jtag_slave_agent_m0_read;                                          // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire          jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                                 // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
	wire          jtag_uart_avalon_jtag_slave_agent_m0_lock;                                          // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                                     // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_write;                                         // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire    [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                                    // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                                  // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [127:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                                   // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                                  // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;                          // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;                            // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                               // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
	wire  [127:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                                // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                               // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;                       // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                         // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;                             // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                              // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;                             // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid;                             // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data;                              // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready;                             // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_ready
	wire   [31:0] intr_capturer_0_avalon_slave_0_agent_m0_readdata;                                   // intr_capturer_0_avalon_slave_0_translator:uav_readdata -> intr_capturer_0_avalon_slave_0_agent:m0_readdata
	wire          intr_capturer_0_avalon_slave_0_agent_m0_waitrequest;                                // intr_capturer_0_avalon_slave_0_translator:uav_waitrequest -> intr_capturer_0_avalon_slave_0_agent:m0_waitrequest
	wire          intr_capturer_0_avalon_slave_0_agent_m0_debugaccess;                                // intr_capturer_0_avalon_slave_0_agent:m0_debugaccess -> intr_capturer_0_avalon_slave_0_translator:uav_debugaccess
	wire   [31:0] intr_capturer_0_avalon_slave_0_agent_m0_address;                                    // intr_capturer_0_avalon_slave_0_agent:m0_address -> intr_capturer_0_avalon_slave_0_translator:uav_address
	wire    [3:0] intr_capturer_0_avalon_slave_0_agent_m0_byteenable;                                 // intr_capturer_0_avalon_slave_0_agent:m0_byteenable -> intr_capturer_0_avalon_slave_0_translator:uav_byteenable
	wire          intr_capturer_0_avalon_slave_0_agent_m0_read;                                       // intr_capturer_0_avalon_slave_0_agent:m0_read -> intr_capturer_0_avalon_slave_0_translator:uav_read
	wire          intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid;                              // intr_capturer_0_avalon_slave_0_translator:uav_readdatavalid -> intr_capturer_0_avalon_slave_0_agent:m0_readdatavalid
	wire          intr_capturer_0_avalon_slave_0_agent_m0_lock;                                       // intr_capturer_0_avalon_slave_0_agent:m0_lock -> intr_capturer_0_avalon_slave_0_translator:uav_lock
	wire   [31:0] intr_capturer_0_avalon_slave_0_agent_m0_writedata;                                  // intr_capturer_0_avalon_slave_0_agent:m0_writedata -> intr_capturer_0_avalon_slave_0_translator:uav_writedata
	wire          intr_capturer_0_avalon_slave_0_agent_m0_write;                                      // intr_capturer_0_avalon_slave_0_agent:m0_write -> intr_capturer_0_avalon_slave_0_translator:uav_write
	wire    [2:0] intr_capturer_0_avalon_slave_0_agent_m0_burstcount;                                 // intr_capturer_0_avalon_slave_0_agent:m0_burstcount -> intr_capturer_0_avalon_slave_0_translator:uav_burstcount
	wire          intr_capturer_0_avalon_slave_0_agent_rf_source_valid;                               // intr_capturer_0_avalon_slave_0_agent:rf_source_valid -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_valid
	wire  [127:0] intr_capturer_0_avalon_slave_0_agent_rf_source_data;                                // intr_capturer_0_avalon_slave_0_agent:rf_source_data -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_data
	wire          intr_capturer_0_avalon_slave_0_agent_rf_source_ready;                               // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rf_source_ready
	wire          intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket;                       // intr_capturer_0_avalon_slave_0_agent:rf_source_startofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket;                         // intr_capturer_0_avalon_slave_0_agent:rf_source_endofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid;                            // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rf_sink_valid
	wire  [127:0] intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data;                             // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rf_sink_data
	wire          intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready;                            // intr_capturer_0_avalon_slave_0_agent:rf_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_ready
	wire          intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket;                    // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_startofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket;                      // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_endofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid;                          // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_valid -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_valid
	wire   [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data;                           // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_data -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_data
	wire          intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready;                          // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_ready
	wire          intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid;                          // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data;                           // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_data
	wire          intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready;                          // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_ready
	wire          cmd_mux_002_src_valid;                                                              // cmd_mux_002:src_valid -> intr_capturer_0_avalon_slave_0_agent:cp_valid
	wire  [126:0] cmd_mux_002_src_data;                                                               // cmd_mux_002:src_data -> intr_capturer_0_avalon_slave_0_agent:cp_data
	wire          cmd_mux_002_src_ready;                                                              // intr_capturer_0_avalon_slave_0_agent:cp_ready -> cmd_mux_002:src_ready
	wire    [4:0] cmd_mux_002_src_channel;                                                            // cmd_mux_002:src_channel -> intr_capturer_0_avalon_slave_0_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                                      // cmd_mux_002:src_startofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                        // cmd_mux_002:src_endofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_endofpacket
	wire   [31:0] sysid_qsys_control_slave_agent_m0_readdata;                                         // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
	wire          sysid_qsys_control_slave_agent_m0_waitrequest;                                      // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
	wire          sysid_qsys_control_slave_agent_m0_debugaccess;                                      // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
	wire   [31:0] sysid_qsys_control_slave_agent_m0_address;                                          // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
	wire    [3:0] sysid_qsys_control_slave_agent_m0_byteenable;                                       // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
	wire          sysid_qsys_control_slave_agent_m0_read;                                             // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
	wire          sysid_qsys_control_slave_agent_m0_readdatavalid;                                    // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
	wire          sysid_qsys_control_slave_agent_m0_lock;                                             // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
	wire   [31:0] sysid_qsys_control_slave_agent_m0_writedata;                                        // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
	wire          sysid_qsys_control_slave_agent_m0_write;                                            // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
	wire    [2:0] sysid_qsys_control_slave_agent_m0_burstcount;                                       // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
	wire          sysid_qsys_control_slave_agent_rf_source_valid;                                     // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
	wire  [127:0] sysid_qsys_control_slave_agent_rf_source_data;                                      // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
	wire          sysid_qsys_control_slave_agent_rf_source_ready;                                     // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
	wire          sysid_qsys_control_slave_agent_rf_source_startofpacket;                             // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
	wire          sysid_qsys_control_slave_agent_rf_source_endofpacket;                               // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_valid;                                  // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
	wire  [127:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data;                                   // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_ready;                                  // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket;                          // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket;                            // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_valid;                                // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent_rdata_fifo:in_valid
	wire   [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data;                                 // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent_rdata_fifo:in_data
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_ready;                                // sysid_qsys_control_slave_agent_rdata_fifo:in_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
	wire          sysid_qsys_control_slave_agent_rdata_fifo_out_valid;                                // sysid_qsys_control_slave_agent_rdata_fifo:out_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] sysid_qsys_control_slave_agent_rdata_fifo_out_data;                                 // sysid_qsys_control_slave_agent_rdata_fifo:out_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
	wire          sysid_qsys_control_slave_agent_rdata_fifo_out_ready;                                // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent_rdata_fifo:out_ready
	wire          hps_0_h2f_axi_master_agent_write_cp_valid;                                          // hps_0_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
	wire  [162:0] hps_0_h2f_axi_master_agent_write_cp_data;                                           // hps_0_h2f_axi_master_agent:write_cp_data -> router:sink_data
	wire          hps_0_h2f_axi_master_agent_write_cp_ready;                                          // router:sink_ready -> hps_0_h2f_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_axi_master_agent_write_cp_startofpacket;                                  // hps_0_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          hps_0_h2f_axi_master_agent_write_cp_endofpacket;                                    // hps_0_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                   // router:src_valid -> cmd_demux:sink_valid
	wire  [162:0] router_src_data;                                                                    // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                   // cmd_demux:sink_ready -> router:src_ready
	wire    [4:0] router_src_channel;                                                                 // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                           // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                             // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          hps_0_h2f_axi_master_agent_read_cp_valid;                                           // hps_0_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
	wire  [162:0] hps_0_h2f_axi_master_agent_read_cp_data;                                            // hps_0_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
	wire          hps_0_h2f_axi_master_agent_read_cp_ready;                                           // router_001:sink_ready -> hps_0_h2f_axi_master_agent:read_cp_ready
	wire          hps_0_h2f_axi_master_agent_read_cp_startofpacket;                                   // hps_0_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          hps_0_h2f_axi_master_agent_read_cp_endofpacket;                                     // hps_0_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                               // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [162:0] router_001_src_data;                                                                // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                               // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [4:0] router_001_src_channel;                                                             // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                                       // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                         // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          fpga_only_master_master_agent_cp_valid;                                             // fpga_only_master_master_agent:cp_valid -> router_002:sink_valid
	wire  [126:0] fpga_only_master_master_agent_cp_data;                                              // fpga_only_master_master_agent:cp_data -> router_002:sink_data
	wire          fpga_only_master_master_agent_cp_ready;                                             // router_002:sink_ready -> fpga_only_master_master_agent:cp_ready
	wire          fpga_only_master_master_agent_cp_startofpacket;                                     // fpga_only_master_master_agent:cp_startofpacket -> router_002:sink_startofpacket
	wire          fpga_only_master_master_agent_cp_endofpacket;                                       // fpga_only_master_master_agent:cp_endofpacket -> router_002:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_valid;                                       // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router_003:sink_valid
	wire  [126:0] hps_0_h2f_lw_axi_master_agent_write_cp_data;                                        // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router_003:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_ready;                                       // router_003:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket;                               // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router_003:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket;                                 // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router_003:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_valid;                                        // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_004:sink_valid
	wire  [126:0] hps_0_h2f_lw_axi_master_agent_read_cp_data;                                         // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_004:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_ready;                                        // router_004:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket;                                // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_004:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket;                                  // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_004:sink_endofpacket
	wire          onchip_memory2_0_s1_agent_rp_valid;                                                 // onchip_memory2_0_s1_agent:rp_valid -> router_005:sink_valid
	wire  [162:0] onchip_memory2_0_s1_agent_rp_data;                                                  // onchip_memory2_0_s1_agent:rp_data -> router_005:sink_data
	wire          onchip_memory2_0_s1_agent_rp_ready;                                                 // router_005:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
	wire          onchip_memory2_0_s1_agent_rp_startofpacket;                                         // onchip_memory2_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          onchip_memory2_0_s1_agent_rp_endofpacket;                                           // onchip_memory2_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                               // router_005:src_valid -> rsp_demux:sink_valid
	wire  [162:0] router_005_src_data;                                                                // router_005:src_data -> rsp_demux:sink_data
	wire          router_005_src_ready;                                                               // rsp_demux:sink_ready -> router_005:src_ready
	wire    [4:0] router_005_src_channel;                                                             // router_005:src_channel -> rsp_demux:sink_channel
	wire          router_005_src_startofpacket;                                                       // router_005:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_005_src_endofpacket;                                                         // router_005:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_valid;                                         // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
	wire  [126:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                                          // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rp_ready;                                         // router_006:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                                 // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                                   // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                               // router_006:src_valid -> rsp_demux_001:sink_valid
	wire  [126:0] router_006_src_data;                                                                // router_006:src_data -> rsp_demux_001:sink_data
	wire          router_006_src_ready;                                                               // rsp_demux_001:sink_ready -> router_006:src_ready
	wire    [4:0] router_006_src_channel;                                                             // router_006:src_channel -> rsp_demux_001:sink_channel
	wire          router_006_src_startofpacket;                                                       // router_006:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_006_src_endofpacket;                                                         // router_006:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rp_valid;                                      // intr_capturer_0_avalon_slave_0_agent:rp_valid -> router_007:sink_valid
	wire  [126:0] intr_capturer_0_avalon_slave_0_agent_rp_data;                                       // intr_capturer_0_avalon_slave_0_agent:rp_data -> router_007:sink_data
	wire          intr_capturer_0_avalon_slave_0_agent_rp_ready;                                      // router_007:sink_ready -> intr_capturer_0_avalon_slave_0_agent:rp_ready
	wire          intr_capturer_0_avalon_slave_0_agent_rp_startofpacket;                              // intr_capturer_0_avalon_slave_0_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          intr_capturer_0_avalon_slave_0_agent_rp_endofpacket;                                // intr_capturer_0_avalon_slave_0_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                               // router_007:src_valid -> rsp_demux_002:sink_valid
	wire  [126:0] router_007_src_data;                                                                // router_007:src_data -> rsp_demux_002:sink_data
	wire          router_007_src_ready;                                                               // rsp_demux_002:sink_ready -> router_007:src_ready
	wire    [4:0] router_007_src_channel;                                                             // router_007:src_channel -> rsp_demux_002:sink_channel
	wire          router_007_src_startofpacket;                                                       // router_007:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_007_src_endofpacket;                                                         // router_007:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rp_valid;                                            // sysid_qsys_control_slave_agent:rp_valid -> router_008:sink_valid
	wire  [126:0] sysid_qsys_control_slave_agent_rp_data;                                             // sysid_qsys_control_slave_agent:rp_data -> router_008:sink_data
	wire          sysid_qsys_control_slave_agent_rp_ready;                                            // router_008:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
	wire          sysid_qsys_control_slave_agent_rp_startofpacket;                                    // sysid_qsys_control_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rp_endofpacket;                                      // sysid_qsys_control_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                                               // router_008:src_valid -> rsp_demux_003:sink_valid
	wire  [126:0] router_008_src_data;                                                                // router_008:src_data -> rsp_demux_003:sink_data
	wire          router_008_src_ready;                                                               // rsp_demux_003:sink_ready -> router_008:src_ready
	wire    [4:0] router_008_src_channel;                                                             // router_008:src_channel -> rsp_demux_003:sink_channel
	wire          router_008_src_startofpacket;                                                       // router_008:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_008_src_endofpacket;                                                         // router_008:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_002_src_valid;                                                               // router_002:src_valid -> fpga_only_master_master_limiter:cmd_sink_valid
	wire  [126:0] router_002_src_data;                                                                // router_002:src_data -> fpga_only_master_master_limiter:cmd_sink_data
	wire          router_002_src_ready;                                                               // fpga_only_master_master_limiter:cmd_sink_ready -> router_002:src_ready
	wire    [4:0] router_002_src_channel;                                                             // router_002:src_channel -> fpga_only_master_master_limiter:cmd_sink_channel
	wire          router_002_src_startofpacket;                                                       // router_002:src_startofpacket -> fpga_only_master_master_limiter:cmd_sink_startofpacket
	wire          router_002_src_endofpacket;                                                         // router_002:src_endofpacket -> fpga_only_master_master_limiter:cmd_sink_endofpacket
	wire  [126:0] fpga_only_master_master_limiter_cmd_src_data;                                       // fpga_only_master_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
	wire          fpga_only_master_master_limiter_cmd_src_ready;                                      // cmd_demux_002:sink_ready -> fpga_only_master_master_limiter:cmd_src_ready
	wire    [4:0] fpga_only_master_master_limiter_cmd_src_channel;                                    // fpga_only_master_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
	wire          fpga_only_master_master_limiter_cmd_src_startofpacket;                              // fpga_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          fpga_only_master_master_limiter_cmd_src_endofpacket;                                // fpga_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          rsp_mux_002_src_valid;                                                              // rsp_mux_002:src_valid -> fpga_only_master_master_limiter:rsp_sink_valid
	wire  [126:0] rsp_mux_002_src_data;                                                               // rsp_mux_002:src_data -> fpga_only_master_master_limiter:rsp_sink_data
	wire          rsp_mux_002_src_ready;                                                              // fpga_only_master_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
	wire    [4:0] rsp_mux_002_src_channel;                                                            // rsp_mux_002:src_channel -> fpga_only_master_master_limiter:rsp_sink_channel
	wire          rsp_mux_002_src_startofpacket;                                                      // rsp_mux_002:src_startofpacket -> fpga_only_master_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                        // rsp_mux_002:src_endofpacket -> fpga_only_master_master_limiter:rsp_sink_endofpacket
	wire          fpga_only_master_master_limiter_rsp_src_valid;                                      // fpga_only_master_master_limiter:rsp_src_valid -> fpga_only_master_master_agent:rp_valid
	wire  [126:0] fpga_only_master_master_limiter_rsp_src_data;                                       // fpga_only_master_master_limiter:rsp_src_data -> fpga_only_master_master_agent:rp_data
	wire          fpga_only_master_master_limiter_rsp_src_ready;                                      // fpga_only_master_master_agent:rp_ready -> fpga_only_master_master_limiter:rsp_src_ready
	wire    [4:0] fpga_only_master_master_limiter_rsp_src_channel;                                    // fpga_only_master_master_limiter:rsp_src_channel -> fpga_only_master_master_agent:rp_channel
	wire          fpga_only_master_master_limiter_rsp_src_startofpacket;                              // fpga_only_master_master_limiter:rsp_src_startofpacket -> fpga_only_master_master_agent:rp_startofpacket
	wire          fpga_only_master_master_limiter_rsp_src_endofpacket;                                // fpga_only_master_master_limiter:rsp_src_endofpacket -> fpga_only_master_master_agent:rp_endofpacket
	wire          router_003_src_valid;                                                               // router_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
	wire  [126:0] router_003_src_data;                                                                // router_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_data
	wire          router_003_src_ready;                                                               // hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router_003:src_ready
	wire    [4:0] router_003_src_channel;                                                             // router_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
	wire          router_003_src_startofpacket;                                                       // router_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
	wire          router_003_src_endofpacket;                                                         // router_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
	wire  [126:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data;                                    // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux_003:sink_data
	wire          hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready;                                   // cmd_demux_003:sink_ready -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_ready
	wire    [4:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel;                                 // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux_003:sink_channel
	wire          hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket;                           // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux_003:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket;                             // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux_003:sink_endofpacket
	wire          rsp_mux_003_src_valid;                                                              // rsp_mux_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
	wire  [126:0] rsp_mux_003_src_data;                                                               // rsp_mux_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_data
	wire          rsp_mux_003_src_ready;                                                              // hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux_003:src_ready
	wire    [4:0] rsp_mux_003_src_channel;                                                            // rsp_mux_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
	wire          rsp_mux_003_src_startofpacket;                                                      // rsp_mux_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
	wire          rsp_mux_003_src_endofpacket;                                                        // rsp_mux_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid;                                   // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
	wire  [126:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data;                                    // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
	wire          hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready;                                   // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_ready
	wire    [4:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel;                                 // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
	wire          hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket;                           // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
	wire          hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket;                             // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
	wire          router_004_src_valid;                                                               // router_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
	wire  [126:0] router_004_src_data;                                                                // router_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_data
	wire          router_004_src_ready;                                                               // hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_004:src_ready
	wire    [4:0] router_004_src_channel;                                                             // router_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
	wire          router_004_src_startofpacket;                                                       // router_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
	wire          router_004_src_endofpacket;                                                         // router_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
	wire  [126:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data;                                    // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_004:sink_data
	wire          hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready;                                   // cmd_demux_004:sink_ready -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_ready
	wire    [4:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel;                                 // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_004:sink_channel
	wire          hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket;                           // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_004:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket;                             // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_004:sink_endofpacket
	wire          rsp_mux_004_src_valid;                                                              // rsp_mux_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
	wire  [126:0] rsp_mux_004_src_data;                                                               // rsp_mux_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_data
	wire          rsp_mux_004_src_ready;                                                              // hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_004:src_ready
	wire    [4:0] rsp_mux_004_src_channel;                                                            // rsp_mux_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
	wire          rsp_mux_004_src_startofpacket;                                                      // rsp_mux_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
	wire          rsp_mux_004_src_endofpacket;                                                        // rsp_mux_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid;                                   // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
	wire  [126:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data;                                    // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
	wire          hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready;                                   // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_ready
	wire    [4:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel;                                 // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
	wire          hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket;                           // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
	wire          hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket;                             // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
	wire          cmd_mux_src_valid;                                                                  // cmd_mux:src_valid -> onchip_memory2_0_s1_burst_adapter:sink0_valid
	wire  [162:0] cmd_mux_src_data;                                                                   // cmd_mux:src_data -> onchip_memory2_0_s1_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                                  // onchip_memory2_0_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire    [4:0] cmd_mux_src_channel;                                                                // cmd_mux:src_channel -> onchip_memory2_0_s1_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                                          // cmd_mux:src_startofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                                            // cmd_mux:src_endofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_endofpacket
	wire          onchip_memory2_0_s1_burst_adapter_source0_valid;                                    // onchip_memory2_0_s1_burst_adapter:source0_valid -> onchip_memory2_0_s1_agent:cp_valid
	wire  [162:0] onchip_memory2_0_s1_burst_adapter_source0_data;                                     // onchip_memory2_0_s1_burst_adapter:source0_data -> onchip_memory2_0_s1_agent:cp_data
	wire          onchip_memory2_0_s1_burst_adapter_source0_ready;                                    // onchip_memory2_0_s1_agent:cp_ready -> onchip_memory2_0_s1_burst_adapter:source0_ready
	wire    [4:0] onchip_memory2_0_s1_burst_adapter_source0_channel;                                  // onchip_memory2_0_s1_burst_adapter:source0_channel -> onchip_memory2_0_s1_agent:cp_channel
	wire          onchip_memory2_0_s1_burst_adapter_source0_startofpacket;                            // onchip_memory2_0_s1_burst_adapter:source0_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
	wire          onchip_memory2_0_s1_burst_adapter_source0_endofpacket;                              // onchip_memory2_0_s1_burst_adapter:source0_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                              // cmd_mux_001:src_valid -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_valid
	wire  [126:0] cmd_mux_001_src_data;                                                               // cmd_mux_001:src_data -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_data
	wire          cmd_mux_001_src_ready;                                                              // jtag_uart_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire    [4:0] cmd_mux_001_src_channel;                                                            // cmd_mux_001:src_channel -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_channel
	wire          cmd_mux_001_src_startofpacket;                                                      // cmd_mux_001:src_startofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                        // cmd_mux_001:src_endofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_endofpacket
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid;                            // jtag_uart_avalon_jtag_slave_burst_adapter:source0_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
	wire  [126:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_data;                             // jtag_uart_avalon_jtag_slave_burst_adapter:source0_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready;                            // jtag_uart_avalon_jtag_slave_agent:cp_ready -> jtag_uart_avalon_jtag_slave_burst_adapter:source0_ready
	wire    [4:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel;                          // jtag_uart_avalon_jtag_slave_burst_adapter:source0_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket;                    // jtag_uart_avalon_jtag_slave_burst_adapter:source0_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket;                      // jtag_uart_avalon_jtag_slave_burst_adapter:source0_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
	wire          cmd_mux_003_src_valid;                                                              // cmd_mux_003:src_valid -> sysid_qsys_control_slave_burst_adapter:sink0_valid
	wire  [126:0] cmd_mux_003_src_data;                                                               // cmd_mux_003:src_data -> sysid_qsys_control_slave_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                                              // sysid_qsys_control_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire    [4:0] cmd_mux_003_src_channel;                                                            // cmd_mux_003:src_channel -> sysid_qsys_control_slave_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                                                      // cmd_mux_003:src_startofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                        // cmd_mux_003:src_endofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_endofpacket
	wire          sysid_qsys_control_slave_burst_adapter_source0_valid;                               // sysid_qsys_control_slave_burst_adapter:source0_valid -> sysid_qsys_control_slave_agent:cp_valid
	wire  [126:0] sysid_qsys_control_slave_burst_adapter_source0_data;                                // sysid_qsys_control_slave_burst_adapter:source0_data -> sysid_qsys_control_slave_agent:cp_data
	wire          sysid_qsys_control_slave_burst_adapter_source0_ready;                               // sysid_qsys_control_slave_agent:cp_ready -> sysid_qsys_control_slave_burst_adapter:source0_ready
	wire    [4:0] sysid_qsys_control_slave_burst_adapter_source0_channel;                             // sysid_qsys_control_slave_burst_adapter:source0_channel -> sysid_qsys_control_slave_agent:cp_channel
	wire          sysid_qsys_control_slave_burst_adapter_source0_startofpacket;                       // sysid_qsys_control_slave_burst_adapter:source0_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
	wire          sysid_qsys_control_slave_burst_adapter_source0_endofpacket;                         // sysid_qsys_control_slave_burst_adapter:source0_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                               // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [162:0] cmd_demux_src0_data;                                                                // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                               // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [4:0] cmd_demux_src0_channel;                                                             // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                       // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                         // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                           // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [162:0] cmd_demux_001_src0_data;                                                            // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                                           // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [4:0] cmd_demux_001_src0_channel;                                                         // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                                   // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                     // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_002_src1_valid;                                                           // cmd_demux_002:src1_valid -> cmd_mux_001:sink0_valid
	wire  [126:0] cmd_demux_002_src1_data;                                                            // cmd_demux_002:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_002_src1_ready;                                                           // cmd_mux_001:sink0_ready -> cmd_demux_002:src1_ready
	wire    [4:0] cmd_demux_002_src1_channel;                                                         // cmd_demux_002:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_002_src1_startofpacket;                                                   // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                                     // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_002_src2_valid;                                                           // cmd_demux_002:src2_valid -> cmd_mux_002:sink0_valid
	wire  [126:0] cmd_demux_002_src2_data;                                                            // cmd_demux_002:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_002_src2_ready;                                                           // cmd_mux_002:sink0_ready -> cmd_demux_002:src2_ready
	wire    [4:0] cmd_demux_002_src2_channel;                                                         // cmd_demux_002:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_002_src2_startofpacket;                                                   // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_002_src2_endofpacket;                                                     // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_002_src3_valid;                                                           // cmd_demux_002:src3_valid -> cmd_mux_003:sink0_valid
	wire  [126:0] cmd_demux_002_src3_data;                                                            // cmd_demux_002:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_002_src3_ready;                                                           // cmd_mux_003:sink0_ready -> cmd_demux_002:src3_ready
	wire    [4:0] cmd_demux_002_src3_channel;                                                         // cmd_demux_002:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_002_src3_startofpacket;                                                   // cmd_demux_002:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_002_src3_endofpacket;                                                     // cmd_demux_002:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_003_src0_valid;                                                           // cmd_demux_003:src0_valid -> cmd_mux_001:sink1_valid
	wire  [126:0] cmd_demux_003_src0_data;                                                            // cmd_demux_003:src0_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_003_src0_ready;                                                           // cmd_mux_001:sink1_ready -> cmd_demux_003:src0_ready
	wire    [4:0] cmd_demux_003_src0_channel;                                                         // cmd_demux_003:src0_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_003_src0_startofpacket;                                                   // cmd_demux_003:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_003_src0_endofpacket;                                                     // cmd_demux_003:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_003_src1_valid;                                                           // cmd_demux_003:src1_valid -> cmd_mux_003:sink1_valid
	wire  [126:0] cmd_demux_003_src1_data;                                                            // cmd_demux_003:src1_data -> cmd_mux_003:sink1_data
	wire          cmd_demux_003_src1_ready;                                                           // cmd_mux_003:sink1_ready -> cmd_demux_003:src1_ready
	wire    [4:0] cmd_demux_003_src1_channel;                                                         // cmd_demux_003:src1_channel -> cmd_mux_003:sink1_channel
	wire          cmd_demux_003_src1_startofpacket;                                                   // cmd_demux_003:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          cmd_demux_003_src1_endofpacket;                                                     // cmd_demux_003:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          cmd_demux_004_src0_valid;                                                           // cmd_demux_004:src0_valid -> cmd_mux_001:sink2_valid
	wire  [126:0] cmd_demux_004_src0_data;                                                            // cmd_demux_004:src0_data -> cmd_mux_001:sink2_data
	wire          cmd_demux_004_src0_ready;                                                           // cmd_mux_001:sink2_ready -> cmd_demux_004:src0_ready
	wire    [4:0] cmd_demux_004_src0_channel;                                                         // cmd_demux_004:src0_channel -> cmd_mux_001:sink2_channel
	wire          cmd_demux_004_src0_startofpacket;                                                   // cmd_demux_004:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
	wire          cmd_demux_004_src0_endofpacket;                                                     // cmd_demux_004:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
	wire          cmd_demux_004_src1_valid;                                                           // cmd_demux_004:src1_valid -> cmd_mux_003:sink2_valid
	wire  [126:0] cmd_demux_004_src1_data;                                                            // cmd_demux_004:src1_data -> cmd_mux_003:sink2_data
	wire          cmd_demux_004_src1_ready;                                                           // cmd_mux_003:sink2_ready -> cmd_demux_004:src1_ready
	wire    [4:0] cmd_demux_004_src1_channel;                                                         // cmd_demux_004:src1_channel -> cmd_mux_003:sink2_channel
	wire          cmd_demux_004_src1_startofpacket;                                                   // cmd_demux_004:src1_startofpacket -> cmd_mux_003:sink2_startofpacket
	wire          cmd_demux_004_src1_endofpacket;                                                     // cmd_demux_004:src1_endofpacket -> cmd_mux_003:sink2_endofpacket
	wire          rsp_demux_src0_valid;                                                               // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [162:0] rsp_demux_src0_data;                                                                // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                               // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [4:0] rsp_demux_src0_channel;                                                             // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                       // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                         // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                               // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [162:0] rsp_demux_src1_data;                                                                // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                                               // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [4:0] rsp_demux_src1_channel;                                                             // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                                       // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                         // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                           // rsp_demux_001:src0_valid -> rsp_mux_002:sink1_valid
	wire  [126:0] rsp_demux_001_src0_data;                                                            // rsp_demux_001:src0_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_001_src0_ready;                                                           // rsp_mux_002:sink1_ready -> rsp_demux_001:src0_ready
	wire    [4:0] rsp_demux_001_src0_channel;                                                         // rsp_demux_001:src0_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                                   // rsp_demux_001:src0_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                     // rsp_demux_001:src0_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                                           // rsp_demux_001:src1_valid -> rsp_mux_003:sink0_valid
	wire  [126:0] rsp_demux_001_src1_data;                                                            // rsp_demux_001:src1_data -> rsp_mux_003:sink0_data
	wire          rsp_demux_001_src1_ready;                                                           // rsp_mux_003:sink0_ready -> rsp_demux_001:src1_ready
	wire    [4:0] rsp_demux_001_src1_channel;                                                         // rsp_demux_001:src1_channel -> rsp_mux_003:sink0_channel
	wire          rsp_demux_001_src1_startofpacket;                                                   // rsp_demux_001:src1_startofpacket -> rsp_mux_003:sink0_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                                     // rsp_demux_001:src1_endofpacket -> rsp_mux_003:sink0_endofpacket
	wire          rsp_demux_001_src2_valid;                                                           // rsp_demux_001:src2_valid -> rsp_mux_004:sink0_valid
	wire  [126:0] rsp_demux_001_src2_data;                                                            // rsp_demux_001:src2_data -> rsp_mux_004:sink0_data
	wire          rsp_demux_001_src2_ready;                                                           // rsp_mux_004:sink0_ready -> rsp_demux_001:src2_ready
	wire    [4:0] rsp_demux_001_src2_channel;                                                         // rsp_demux_001:src2_channel -> rsp_mux_004:sink0_channel
	wire          rsp_demux_001_src2_startofpacket;                                                   // rsp_demux_001:src2_startofpacket -> rsp_mux_004:sink0_startofpacket
	wire          rsp_demux_001_src2_endofpacket;                                                     // rsp_demux_001:src2_endofpacket -> rsp_mux_004:sink0_endofpacket
	wire          rsp_demux_002_src0_valid;                                                           // rsp_demux_002:src0_valid -> rsp_mux_002:sink2_valid
	wire  [126:0] rsp_demux_002_src0_data;                                                            // rsp_demux_002:src0_data -> rsp_mux_002:sink2_data
	wire          rsp_demux_002_src0_ready;                                                           // rsp_mux_002:sink2_ready -> rsp_demux_002:src0_ready
	wire    [4:0] rsp_demux_002_src0_channel;                                                         // rsp_demux_002:src0_channel -> rsp_mux_002:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                                   // rsp_demux_002:src0_startofpacket -> rsp_mux_002:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                     // rsp_demux_002:src0_endofpacket -> rsp_mux_002:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                           // rsp_demux_003:src0_valid -> rsp_mux_002:sink3_valid
	wire  [126:0] rsp_demux_003_src0_data;                                                            // rsp_demux_003:src0_data -> rsp_mux_002:sink3_data
	wire          rsp_demux_003_src0_ready;                                                           // rsp_mux_002:sink3_ready -> rsp_demux_003:src0_ready
	wire    [4:0] rsp_demux_003_src0_channel;                                                         // rsp_demux_003:src0_channel -> rsp_mux_002:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                                   // rsp_demux_003:src0_startofpacket -> rsp_mux_002:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                     // rsp_demux_003:src0_endofpacket -> rsp_mux_002:sink3_endofpacket
	wire          rsp_demux_003_src1_valid;                                                           // rsp_demux_003:src1_valid -> rsp_mux_003:sink1_valid
	wire  [126:0] rsp_demux_003_src1_data;                                                            // rsp_demux_003:src1_data -> rsp_mux_003:sink1_data
	wire          rsp_demux_003_src1_ready;                                                           // rsp_mux_003:sink1_ready -> rsp_demux_003:src1_ready
	wire    [4:0] rsp_demux_003_src1_channel;                                                         // rsp_demux_003:src1_channel -> rsp_mux_003:sink1_channel
	wire          rsp_demux_003_src1_startofpacket;                                                   // rsp_demux_003:src1_startofpacket -> rsp_mux_003:sink1_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                                                     // rsp_demux_003:src1_endofpacket -> rsp_mux_003:sink1_endofpacket
	wire          rsp_demux_003_src2_valid;                                                           // rsp_demux_003:src2_valid -> rsp_mux_004:sink1_valid
	wire  [126:0] rsp_demux_003_src2_data;                                                            // rsp_demux_003:src2_data -> rsp_mux_004:sink1_data
	wire          rsp_demux_003_src2_ready;                                                           // rsp_mux_004:sink1_ready -> rsp_demux_003:src2_ready
	wire    [4:0] rsp_demux_003_src2_channel;                                                         // rsp_demux_003:src2_channel -> rsp_mux_004:sink1_channel
	wire          rsp_demux_003_src2_startofpacket;                                                   // rsp_demux_003:src2_startofpacket -> rsp_mux_004:sink1_startofpacket
	wire          rsp_demux_003_src2_endofpacket;                                                     // rsp_demux_003:src2_endofpacket -> rsp_mux_004:sink1_endofpacket
	wire          cmd_demux_002_src0_valid;                                                           // cmd_demux_002:src0_valid -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_valid
	wire  [126:0] cmd_demux_002_src0_data;                                                            // cmd_demux_002:src0_data -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_data
	wire          cmd_demux_002_src0_ready;                                                           // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
	wire    [4:0] cmd_demux_002_src0_channel;                                                         // cmd_demux_002:src0_channel -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_channel
	wire          cmd_demux_002_src0_startofpacket;                                                   // cmd_demux_002:src0_startofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                                     // cmd_demux_002:src0_endofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_endofpacket
	wire          fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid;         // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_valid -> cmd_mux:sink2_valid
	wire  [162:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data;          // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_data -> cmd_mux:sink2_data
	wire          fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready;         // cmd_mux:sink2_ready -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_ready
	wire    [4:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel;       // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_channel -> cmd_mux:sink2_channel
	wire          fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink2_startofpacket
	wire          fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket;   // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink2_endofpacket
	wire          rsp_demux_src2_valid;                                                               // rsp_demux:src2_valid -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_valid
	wire  [162:0] rsp_demux_src2_data;                                                                // rsp_demux:src2_data -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_data
	wire          rsp_demux_src2_ready;                                                               // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_ready -> rsp_demux:src2_ready
	wire    [4:0] rsp_demux_src2_channel;                                                             // rsp_demux:src2_channel -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_channel
	wire          rsp_demux_src2_startofpacket;                                                       // rsp_demux:src2_startofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_src2_endofpacket;                                                         // rsp_demux:src2_endofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_endofpacket
	wire          onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid;         // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_valid -> rsp_mux_002:sink0_valid
	wire  [126:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data;          // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_data -> rsp_mux_002:sink0_data
	wire          onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready;         // rsp_mux_002:sink0_ready -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_ready
	wire    [4:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel;       // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_channel -> rsp_mux_002:sink0_channel
	wire          onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket;   // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire    [4:0] fpga_only_master_master_limiter_cmd_valid_data;                                     // fpga_only_master_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
	wire    [4:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data;                                  // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux_003:sink_valid
	wire    [4:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data;                                  // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_004:sink_valid

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) fpga_only_master_master_translator (
		.clk                    (clk_0_clk_clk),                                                              //                       clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                        //                     reset.reset
		.uav_address            (fpga_only_master_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (fpga_only_master_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (fpga_only_master_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (fpga_only_master_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (fpga_only_master_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (fpga_only_master_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (fpga_only_master_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (fpga_only_master_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (fpga_only_master_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (fpga_only_master_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (fpga_only_master_master_byteenable),                                         //                          .byteenable
		.av_read                (fpga_only_master_master_read),                                               //                          .read
		.av_readdata            (fpga_only_master_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (fpga_only_master_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (fpga_only_master_master_write),                                              //                          .write
		.av_writedata           (fpga_only_master_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                       //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                       //               (terminated)
		.av_begintransfer       (1'b0),                                                                       //               (terminated)
		.av_chipselect          (1'b0),                                                                       //               (terminated)
		.av_lock                (1'b0),                                                                       //               (terminated)
		.av_debugaccess         (1'b0),                                                                       //               (terminated)
		.uav_clken              (),                                                                           //               (terminated)
		.av_clken               (1'b1),                                                                       //               (terminated)
		.uav_response           (2'b00),                                                                      //               (terminated)
		.av_response            (),                                                                           //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                       //               (terminated)
		.av_writeresponsevalid  ()                                                                            //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (4),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_memory2_0_s1_translator (
		.clk                    (clk_0_clk_clk),                                       //                      clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_memory2_0_s1_agent_m0_address),                // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_memory2_0_s1_agent_m0_burstcount),             //                         .burstcount
		.uav_read               (onchip_memory2_0_s1_agent_m0_read),                   //                         .read
		.uav_write              (onchip_memory2_0_s1_agent_m0_write),                  //                         .write
		.uav_waitrequest        (onchip_memory2_0_s1_agent_m0_waitrequest),            //                         .waitrequest
		.uav_readdatavalid      (onchip_memory2_0_s1_agent_m0_readdatavalid),          //                         .readdatavalid
		.uav_byteenable         (onchip_memory2_0_s1_agent_m0_byteenable),             //                         .byteenable
		.uav_readdata           (onchip_memory2_0_s1_agent_m0_readdata),               //                         .readdata
		.uav_writedata          (onchip_memory2_0_s1_agent_m0_writedata),              //                         .writedata
		.uav_lock               (onchip_memory2_0_s1_agent_m0_lock),                   //                         .lock
		.uav_debugaccess        (onchip_memory2_0_s1_agent_m0_debugaccess),            //                         .debugaccess
		.av_address             (onchip_memory2_0_s1_address),                         //      avalon_anti_slave_0.address
		.av_write               (onchip_memory2_0_s1_write),                           //                         .write
		.av_readdata            (onchip_memory2_0_s1_readdata),                        //                         .readdata
		.av_writedata           (onchip_memory2_0_s1_writedata),                       //                         .writedata
		.av_byteenable          (onchip_memory2_0_s1_byteenable),                      //                         .byteenable
		.av_chipselect          (onchip_memory2_0_s1_chipselect),                      //                         .chipselect
		.av_clken               (onchip_memory2_0_s1_clken),                           //                         .clken
		.av_read                (),                                                    //              (terminated)
		.av_begintransfer       (),                                                    //              (terminated)
		.av_beginbursttransfer  (),                                                    //              (terminated)
		.av_burstcount          (),                                                    //              (terminated)
		.av_readdatavalid       (1'b0),                                                //              (terminated)
		.av_waitrequest         (1'b0),                                                //              (terminated)
		.av_writebyteenable     (),                                                    //              (terminated)
		.av_lock                (),                                                    //              (terminated)
		.uav_clken              (1'b0),                                                //              (terminated)
		.av_debugaccess         (),                                                    //              (terminated)
		.av_outputenable        (),                                                    //              (terminated)
		.uav_response           (),                                                    //              (terminated)
		.av_response            (2'b00),                                               //              (terminated)
		.uav_writeresponsevalid (),                                                    //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                    (clk_0_clk_clk),                                       //                      clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),           //                         .read
		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),          //                         .write
		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),      //                         .writedata
		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (jtag_uart_avalon_jtag_slave_address),                 //      avalon_anti_slave_0.address
		.av_write               (jtag_uart_avalon_jtag_slave_write),                   //                         .write
		.av_read                (jtag_uart_avalon_jtag_slave_read),                    //                         .read
		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),                //                         .readdata
		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),               //                         .writedata
		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),             //                         .waitrequest
		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),              //                         .chipselect
		.av_begintransfer       (),                                                    //              (terminated)
		.av_beginbursttransfer  (),                                                    //              (terminated)
		.av_burstcount          (),                                                    //              (terminated)
		.av_byteenable          (),                                                    //              (terminated)
		.av_readdatavalid       (1'b0),                                                //              (terminated)
		.av_writebyteenable     (),                                                    //              (terminated)
		.av_lock                (),                                                    //              (terminated)
		.av_clken               (),                                                    //              (terminated)
		.uav_clken              (1'b0),                                                //              (terminated)
		.av_debugaccess         (),                                                    //              (terminated)
		.av_outputenable        (),                                                    //              (terminated)
		.uav_response           (),                                                    //              (terminated)
		.av_response            (2'b00),                                               //              (terminated)
		.uav_writeresponsevalid (),                                                    //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) intr_capturer_0_avalon_slave_0_translator (
		.clk                    (clk_0_clk_clk),                                         //                      clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),   //                    reset.reset
		.uav_address            (intr_capturer_0_avalon_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (intr_capturer_0_avalon_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (intr_capturer_0_avalon_slave_0_agent_m0_read),          //                         .read
		.uav_write              (intr_capturer_0_avalon_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest        (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (intr_capturer_0_avalon_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (intr_capturer_0_avalon_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (intr_capturer_0_avalon_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (intr_capturer_0_avalon_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (intr_capturer_0_avalon_slave_0_address),                //      avalon_anti_slave_0.address
		.av_read                (intr_capturer_0_avalon_slave_0_read),                   //                         .read
		.av_readdata            (intr_capturer_0_avalon_slave_0_readdata),               //                         .readdata
		.av_write               (),                                                      //              (terminated)
		.av_writedata           (),                                                      //              (terminated)
		.av_begintransfer       (),                                                      //              (terminated)
		.av_beginbursttransfer  (),                                                      //              (terminated)
		.av_burstcount          (),                                                      //              (terminated)
		.av_byteenable          (),                                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                                  //              (terminated)
		.av_waitrequest         (1'b0),                                                  //              (terminated)
		.av_writebyteenable     (),                                                      //              (terminated)
		.av_lock                (),                                                      //              (terminated)
		.av_chipselect          (),                                                      //              (terminated)
		.av_clken               (),                                                      //              (terminated)
		.uav_clken              (1'b0),                                                  //              (terminated)
		.av_debugaccess         (),                                                      //              (terminated)
		.av_outputenable        (),                                                      //              (terminated)
		.uav_response           (),                                                      //              (terminated)
		.av_response            (2'b00),                                                 //              (terminated)
		.uav_writeresponsevalid (),                                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sysid_qsys_control_slave_translator (
		.clk                    (clk_0_clk_clk),                                       //                      clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sysid_qsys_control_slave_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (sysid_qsys_control_slave_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (sysid_qsys_control_slave_agent_m0_read),              //                         .read
		.uav_write              (sysid_qsys_control_slave_agent_m0_write),             //                         .write
		.uav_waitrequest        (sysid_qsys_control_slave_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (sysid_qsys_control_slave_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (sysid_qsys_control_slave_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (sysid_qsys_control_slave_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (sysid_qsys_control_slave_agent_m0_writedata),         //                         .writedata
		.uav_lock               (sysid_qsys_control_slave_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (sysid_qsys_control_slave_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (sysid_qsys_control_slave_address),                    //      avalon_anti_slave_0.address
		.av_readdata            (sysid_qsys_control_slave_readdata),                   //                         .readdata
		.av_write               (),                                                    //              (terminated)
		.av_read                (),                                                    //              (terminated)
		.av_writedata           (),                                                    //              (terminated)
		.av_begintransfer       (),                                                    //              (terminated)
		.av_beginbursttransfer  (),                                                    //              (terminated)
		.av_burstcount          (),                                                    //              (terminated)
		.av_byteenable          (),                                                    //              (terminated)
		.av_readdatavalid       (1'b0),                                                //              (terminated)
		.av_waitrequest         (1'b0),                                                //              (terminated)
		.av_writebyteenable     (),                                                    //              (terminated)
		.av_lock                (),                                                    //              (terminated)
		.av_chipselect          (),                                                    //              (terminated)
		.av_clken               (),                                                    //              (terminated)
		.uav_clken              (1'b0),                                                //              (terminated)
		.av_debugaccess         (),                                                    //              (terminated)
		.av_outputenable        (),                                                    //              (terminated)
		.uav_response           (),                                                    //              (terminated)
		.av_response            (2'b00),                                               //              (terminated)
		.uav_writeresponsevalid (),                                                    //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                 //              (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (30),
		.RDATA_WIDTH               (64),
		.WDATA_WIDTH               (64),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (133),
		.PKT_CACHE_H               (157),
		.PKT_CACHE_L               (154),
		.PKT_ADDR_SIDEBAND_H       (131),
		.PKT_ADDR_SIDEBAND_L       (131),
		.PKT_PROTECTION_H          (153),
		.PKT_PROTECTION_L          (151),
		.PKT_BURST_SIZE_H          (128),
		.PKT_BURST_SIZE_L          (126),
		.PKT_BURST_TYPE_H          (130),
		.PKT_BURST_TYPE_L          (129),
		.PKT_RESPONSE_STATUS_L     (158),
		.PKT_RESPONSE_STATUS_H     (159),
		.PKT_BURSTWRAP_H           (125),
		.PKT_BURSTWRAP_L           (118),
		.PKT_BYTE_CNT_H            (117),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_TRANS_LOCK            (108),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (136),
		.PKT_SRC_ID_L              (135),
		.PKT_DEST_ID_H             (138),
		.PKT_DEST_ID_L             (137),
		.PKT_THREAD_ID_H           (150),
		.PKT_THREAD_ID_L           (139),
		.PKT_QOS_L                 (134),
		.PKT_QOS_H                 (134),
		.PKT_ORI_BURST_SIZE_L      (160),
		.PKT_ORI_BURST_SIZE_H      (162),
		.PKT_DATA_SIDEBAND_H       (132),
		.PKT_DATA_SIDEBAND_L       (132),
		.ST_DATA_W                 (163),
		.ST_CHANNEL_W              (5),
		.ID                        (1)
	) hps_0_h2f_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                     //              clk.clk
		.aresetn                (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_axi_master_agent_write_cp_valid),                         //         write_cp.valid
		.write_cp_data          (hps_0_h2f_axi_master_agent_write_cp_data),                          //                 .data
		.write_cp_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket),                 //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_axi_master_agent_write_cp_endofpacket),                   //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_axi_master_agent_write_cp_ready),                         //                 .ready
		.write_rp_valid         (rsp_mux_src_valid),                                                 //         write_rp.valid
		.write_rp_data          (rsp_mux_src_data),                                                  //                 .data
		.write_rp_channel       (rsp_mux_src_channel),                                               //                 .channel
		.write_rp_startofpacket (rsp_mux_src_startofpacket),                                         //                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_src_endofpacket),                                           //                 .endofpacket
		.write_rp_ready         (rsp_mux_src_ready),                                                 //                 .ready
		.read_cp_valid          (hps_0_h2f_axi_master_agent_read_cp_valid),                          //          read_cp.valid
		.read_cp_data           (hps_0_h2f_axi_master_agent_read_cp_data),                           //                 .data
		.read_cp_startofpacket  (hps_0_h2f_axi_master_agent_read_cp_startofpacket),                  //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_axi_master_agent_read_cp_endofpacket),                    //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_axi_master_agent_read_cp_ready),                          //                 .ready
		.read_rp_valid          (rsp_mux_001_src_valid),                                             //          read_rp.valid
		.read_rp_data           (rsp_mux_001_src_data),                                              //                 .data
		.read_rp_channel        (rsp_mux_001_src_channel),                                           //                 .channel
		.read_rp_startofpacket  (rsp_mux_001_src_startofpacket),                                     //                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_001_src_endofpacket),                                       //                 .endofpacket
		.read_rp_ready          (rsp_mux_001_src_ready),                                             //                 .ready
		.awid                   (hps_0_h2f_axi_master_awid),                                         // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_axi_master_awaddr),                                       //                 .awaddr
		.awlen                  (hps_0_h2f_axi_master_awlen),                                        //                 .awlen
		.awsize                 (hps_0_h2f_axi_master_awsize),                                       //                 .awsize
		.awburst                (hps_0_h2f_axi_master_awburst),                                      //                 .awburst
		.awlock                 (hps_0_h2f_axi_master_awlock),                                       //                 .awlock
		.awcache                (hps_0_h2f_axi_master_awcache),                                      //                 .awcache
		.awprot                 (hps_0_h2f_axi_master_awprot),                                       //                 .awprot
		.awvalid                (hps_0_h2f_axi_master_awvalid),                                      //                 .awvalid
		.awready                (hps_0_h2f_axi_master_awready),                                      //                 .awready
		.wid                    (hps_0_h2f_axi_master_wid),                                          //                 .wid
		.wdata                  (hps_0_h2f_axi_master_wdata),                                        //                 .wdata
		.wstrb                  (hps_0_h2f_axi_master_wstrb),                                        //                 .wstrb
		.wlast                  (hps_0_h2f_axi_master_wlast),                                        //                 .wlast
		.wvalid                 (hps_0_h2f_axi_master_wvalid),                                       //                 .wvalid
		.wready                 (hps_0_h2f_axi_master_wready),                                       //                 .wready
		.bid                    (hps_0_h2f_axi_master_bid),                                          //                 .bid
		.bresp                  (hps_0_h2f_axi_master_bresp),                                        //                 .bresp
		.bvalid                 (hps_0_h2f_axi_master_bvalid),                                       //                 .bvalid
		.bready                 (hps_0_h2f_axi_master_bready),                                       //                 .bready
		.arid                   (hps_0_h2f_axi_master_arid),                                         //                 .arid
		.araddr                 (hps_0_h2f_axi_master_araddr),                                       //                 .araddr
		.arlen                  (hps_0_h2f_axi_master_arlen),                                        //                 .arlen
		.arsize                 (hps_0_h2f_axi_master_arsize),                                       //                 .arsize
		.arburst                (hps_0_h2f_axi_master_arburst),                                      //                 .arburst
		.arlock                 (hps_0_h2f_axi_master_arlock),                                       //                 .arlock
		.arcache                (hps_0_h2f_axi_master_arcache),                                      //                 .arcache
		.arprot                 (hps_0_h2f_axi_master_arprot),                                       //                 .arprot
		.arvalid                (hps_0_h2f_axi_master_arvalid),                                      //                 .arvalid
		.arready                (hps_0_h2f_axi_master_arready),                                      //                 .arready
		.rid                    (hps_0_h2f_axi_master_rid),                                          //                 .rid
		.rdata                  (hps_0_h2f_axi_master_rdata),                                        //                 .rdata
		.rresp                  (hps_0_h2f_axi_master_rresp),                                        //                 .rresp
		.rlast                  (hps_0_h2f_axi_master_rlast),                                        //                 .rlast
		.rvalid                 (hps_0_h2f_axi_master_rvalid),                                       //                 .rvalid
		.rready                 (hps_0_h2f_axi_master_rready),                                       //                 .rready
		.awuser                 (1'b0),                                                              //      (terminated)
		.aruser                 (1'b0),                                                              //      (terminated)
		.awqos                  (4'b0000),                                                           //      (terminated)
		.arqos                  (4'b0000),                                                           //      (terminated)
		.awregion               (4'b0000),                                                           //      (terminated)
		.arregion               (4'b0000),                                                           //      (terminated)
		.wuser                  (1'b0),                                                              //      (terminated)
		.ruser                  (),                                                                  //      (terminated)
		.buser                  ()                                                                   //      (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_QOS_H                 (98),
		.PKT_QOS_L                 (98),
		.PKT_DATA_SIDEBAND_H       (96),
		.PKT_DATA_SIDEBAND_L       (96),
		.PKT_ADDR_SIDEBAND_H       (95),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_CACHE_H               (121),
		.PKT_CACHE_L               (118),
		.PKT_THREAD_ID_H           (114),
		.PKT_THREAD_ID_L           (103),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (255),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) fpga_only_master_master_agent (
		.clk                   (clk_0_clk_clk),                                                              //       clk.clk
		.reset                 (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                        // clk_reset.reset
		.av_address            (fpga_only_master_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (fpga_only_master_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (fpga_only_master_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (fpga_only_master_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (fpga_only_master_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (fpga_only_master_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (fpga_only_master_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (fpga_only_master_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (fpga_only_master_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (fpga_only_master_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (fpga_only_master_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (fpga_only_master_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (fpga_only_master_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (fpga_only_master_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (fpga_only_master_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (fpga_only_master_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (fpga_only_master_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (fpga_only_master_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (fpga_only_master_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                           // (terminated)
		.av_writeresponsevalid ()                                                                            // (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (21),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (97),
		.PKT_CACHE_H               (121),
		.PKT_CACHE_L               (118),
		.PKT_ADDR_SIDEBAND_H       (95),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_THREAD_ID_H           (114),
		.PKT_THREAD_ID_L           (103),
		.PKT_QOS_L                 (98),
		.PKT_QOS_H                 (98),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_DATA_SIDEBAND_H       (96),
		.PKT_DATA_SIDEBAND_L       (96),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.ID                        (2)
	) hps_0_h2f_lw_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                     //              clk.clk
		.aresetn                (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                      //         write_cp.valid
		.write_cp_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                       //                 .data
		.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),              //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                      //                 .ready
		.write_rp_valid         (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid),                  //         write_rp.valid
		.write_rp_data          (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data),                   //                 .data
		.write_rp_channel       (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel),                //                 .channel
		.write_rp_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket),          //                 .startofpacket
		.write_rp_endofpacket   (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket),            //                 .endofpacket
		.write_rp_ready         (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready),                  //                 .ready
		.read_cp_valid          (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                       //          read_cp.valid
		.read_cp_data           (hps_0_h2f_lw_axi_master_agent_read_cp_data),                        //                 .data
		.read_cp_startofpacket  (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),               //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                 //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                       //                 .ready
		.read_rp_valid          (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid),                  //          read_rp.valid
		.read_rp_data           (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data),                   //                 .data
		.read_rp_channel        (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel),                //                 .channel
		.read_rp_startofpacket  (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket),          //                 .startofpacket
		.read_rp_endofpacket    (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket),            //                 .endofpacket
		.read_rp_ready          (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready),                  //                 .ready
		.awid                   (hps_0_h2f_lw_axi_master_awid),                                      // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_lw_axi_master_awaddr),                                    //                 .awaddr
		.awlen                  (hps_0_h2f_lw_axi_master_awlen),                                     //                 .awlen
		.awsize                 (hps_0_h2f_lw_axi_master_awsize),                                    //                 .awsize
		.awburst                (hps_0_h2f_lw_axi_master_awburst),                                   //                 .awburst
		.awlock                 (hps_0_h2f_lw_axi_master_awlock),                                    //                 .awlock
		.awcache                (hps_0_h2f_lw_axi_master_awcache),                                   //                 .awcache
		.awprot                 (hps_0_h2f_lw_axi_master_awprot),                                    //                 .awprot
		.awvalid                (hps_0_h2f_lw_axi_master_awvalid),                                   //                 .awvalid
		.awready                (hps_0_h2f_lw_axi_master_awready),                                   //                 .awready
		.wid                    (hps_0_h2f_lw_axi_master_wid),                                       //                 .wid
		.wdata                  (hps_0_h2f_lw_axi_master_wdata),                                     //                 .wdata
		.wstrb                  (hps_0_h2f_lw_axi_master_wstrb),                                     //                 .wstrb
		.wlast                  (hps_0_h2f_lw_axi_master_wlast),                                     //                 .wlast
		.wvalid                 (hps_0_h2f_lw_axi_master_wvalid),                                    //                 .wvalid
		.wready                 (hps_0_h2f_lw_axi_master_wready),                                    //                 .wready
		.bid                    (hps_0_h2f_lw_axi_master_bid),                                       //                 .bid
		.bresp                  (hps_0_h2f_lw_axi_master_bresp),                                     //                 .bresp
		.bvalid                 (hps_0_h2f_lw_axi_master_bvalid),                                    //                 .bvalid
		.bready                 (hps_0_h2f_lw_axi_master_bready),                                    //                 .bready
		.arid                   (hps_0_h2f_lw_axi_master_arid),                                      //                 .arid
		.araddr                 (hps_0_h2f_lw_axi_master_araddr),                                    //                 .araddr
		.arlen                  (hps_0_h2f_lw_axi_master_arlen),                                     //                 .arlen
		.arsize                 (hps_0_h2f_lw_axi_master_arsize),                                    //                 .arsize
		.arburst                (hps_0_h2f_lw_axi_master_arburst),                                   //                 .arburst
		.arlock                 (hps_0_h2f_lw_axi_master_arlock),                                    //                 .arlock
		.arcache                (hps_0_h2f_lw_axi_master_arcache),                                   //                 .arcache
		.arprot                 (hps_0_h2f_lw_axi_master_arprot),                                    //                 .arprot
		.arvalid                (hps_0_h2f_lw_axi_master_arvalid),                                   //                 .arvalid
		.arready                (hps_0_h2f_lw_axi_master_arready),                                   //                 .arready
		.rid                    (hps_0_h2f_lw_axi_master_rid),                                       //                 .rid
		.rdata                  (hps_0_h2f_lw_axi_master_rdata),                                     //                 .rdata
		.rresp                  (hps_0_h2f_lw_axi_master_rresp),                                     //                 .rresp
		.rlast                  (hps_0_h2f_lw_axi_master_rlast),                                     //                 .rlast
		.rvalid                 (hps_0_h2f_lw_axi_master_rvalid),                                    //                 .rvalid
		.rready                 (hps_0_h2f_lw_axi_master_rready),                                    //                 .rready
		.awuser                 (1'b0),                                                              //      (terminated)
		.aruser                 (1'b0),                                                              //      (terminated)
		.awqos                  (4'b0000),                                                           //      (terminated)
		.arqos                  (4'b0000),                                                           //      (terminated)
		.awregion               (4'b0000),                                                           //      (terminated)
		.arregion               (4'b0000),                                                           //      (terminated)
		.wuser                  (1'b0),                                                              //      (terminated)
		.ruser                  (),                                                                  //      (terminated)
		.buser                  ()                                                                   //      (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (162),
		.PKT_ORI_BURST_SIZE_L      (160),
		.PKT_RESPONSE_STATUS_H     (159),
		.PKT_RESPONSE_STATUS_L     (158),
		.PKT_BURST_SIZE_H          (128),
		.PKT_BURST_SIZE_L          (126),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (133),
		.PKT_PROTECTION_H          (153),
		.PKT_PROTECTION_L          (151),
		.PKT_BURSTWRAP_H           (125),
		.PKT_BURSTWRAP_L           (118),
		.PKT_BYTE_CNT_H            (117),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (136),
		.PKT_SRC_ID_L              (135),
		.PKT_DEST_ID_H             (138),
		.PKT_DEST_ID_L             (137),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (163),
		.AVS_BURSTCOUNT_W          (4),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) onchip_memory2_0_s1_agent (
		.clk                     (clk_0_clk_clk),                                           //             clk.clk
		.reset                   (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),     //       clk_reset.reset
		.m0_address              (onchip_memory2_0_s1_agent_m0_address),                    //              m0.address
		.m0_burstcount           (onchip_memory2_0_s1_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (onchip_memory2_0_s1_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (onchip_memory2_0_s1_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (onchip_memory2_0_s1_agent_m0_lock),                       //                .lock
		.m0_readdata             (onchip_memory2_0_s1_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (onchip_memory2_0_s1_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (onchip_memory2_0_s1_agent_m0_read),                       //                .read
		.m0_waitrequest          (onchip_memory2_0_s1_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (onchip_memory2_0_s1_agent_m0_writedata),                  //                .writedata
		.m0_write                (onchip_memory2_0_s1_agent_m0_write),                      //                .write
		.rp_endofpacket          (onchip_memory2_0_s1_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (onchip_memory2_0_s1_agent_rp_ready),                      //                .ready
		.rp_valid                (onchip_memory2_0_s1_agent_rp_valid),                      //                .valid
		.rp_data                 (onchip_memory2_0_s1_agent_rp_data),                       //                .data
		.rp_startofpacket        (onchip_memory2_0_s1_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (onchip_memory2_0_s1_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (onchip_memory2_0_s1_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (onchip_memory2_0_s1_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (onchip_memory2_0_s1_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (onchip_memory2_0_s1_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (onchip_memory2_0_s1_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (onchip_memory2_0_s1_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (onchip_memory2_0_s1_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (onchip_memory2_0_s1_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (onchip_memory2_0_s1_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (onchip_memory2_0_s1_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (onchip_memory2_0_s1_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (onchip_memory2_0_s1_agent_rdata_fifo_out_ready),          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (onchip_memory2_0_s1_agent_rdata_fifo_out_valid),          //                .valid
		.rdata_fifo_sink_data    (onchip_memory2_0_s1_agent_rdata_fifo_out_data),           //                .data
		.rdata_fifo_src_ready    (onchip_memory2_0_s1_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory2_0_s1_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (onchip_memory2_0_s1_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                   //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                     //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (164),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_0_s1_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                        //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),  // clk_reset.reset
		.in_data           (onchip_memory2_0_s1_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_memory2_0_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_memory2_0_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_memory2_0_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_memory2_0_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_memory2_0_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_memory2_0_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_memory2_0_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (66),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_0_s1_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                       //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (onchip_memory2_0_s1_agent_rdata_fifo_src_data),       //        in.data
		.in_valid          (onchip_memory2_0_s1_agent_rdata_fifo_src_valid),      //          .valid
		.in_ready          (onchip_memory2_0_s1_agent_rdata_fifo_src_ready),      //          .ready
		.out_data          (onchip_memory2_0_s1_agent_rdata_fifo_out_data),       //       out.data
		.out_valid         (onchip_memory2_0_s1_agent_rdata_fifo_out_valid),      //          .valid
		.out_ready         (onchip_memory2_0_s1_agent_rdata_fifo_out_ready),      //          .ready
		.csr_address       (2'b00),                                               // (terminated)
		.csr_read          (1'b0),                                                // (terminated)
		.csr_write         (1'b0),                                                // (terminated)
		.csr_readdata      (),                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated)
		.almost_full_data  (),                                                    // (terminated)
		.almost_empty_data (),                                                    // (terminated)
		.in_startofpacket  (1'b0),                                                // (terminated)
		.in_endofpacket    (1'b0),                                                // (terminated)
		.out_startofpacket (),                                                    // (terminated)
		.out_endofpacket   (),                                                    // (terminated)
		.in_empty          (1'b0),                                                // (terminated)
		.out_empty         (),                                                    // (terminated)
		.in_error          (1'b0),                                                // (terminated)
		.out_error         (),                                                    // (terminated)
		.in_channel        (1'b0),                                                // (terminated)
		.out_channel       ()                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (127),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) jtag_uart_avalon_jtag_slave_agent (
		.clk                     (clk_0_clk_clk),                                                   //             clk.clk
		.reset                   (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),             //       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready),          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid),          //                .valid
		.rdata_fifo_sink_data    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data),           //                .data
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (128),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                                //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),          // clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated)
		.csr_read          (1'b0),                                                         // (terminated)
		.csr_write         (1'b0),                                                         // (terminated)
		.csr_readdata      (),                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
		.almost_full_data  (),                                                             // (terminated)
		.almost_empty_data (),                                                             // (terminated)
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.in_error          (1'b0),                                                         // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_channel        (1'b0),                                                         // (terminated)
		.out_channel       ()                                                              // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_uart_avalon_jtag_slave_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                          //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),    // clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                  // (terminated)
		.csr_read          (1'b0),                                                   // (terminated)
		.csr_write         (1'b0),                                                   // (terminated)
		.csr_readdata      (),                                                       // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated)
		.almost_full_data  (),                                                       // (terminated)
		.almost_empty_data (),                                                       // (terminated)
		.in_startofpacket  (1'b0),                                                   // (terminated)
		.in_endofpacket    (1'b0),                                                   // (terminated)
		.out_startofpacket (),                                                       // (terminated)
		.out_endofpacket   (),                                                       // (terminated)
		.in_empty          (1'b0),                                                   // (terminated)
		.out_empty         (),                                                       // (terminated)
		.in_error          (1'b0),                                                   // (terminated)
		.out_error         (),                                                       // (terminated)
		.in_channel        (1'b0),                                                   // (terminated)
		.out_channel       ()                                                        // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (127),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) intr_capturer_0_avalon_slave_0_agent (
		.clk                     (clk_0_clk_clk),                                                   //             clk.clk
		.reset                   (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),             //       clk_reset.reset
		.m0_address              (intr_capturer_0_avalon_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (intr_capturer_0_avalon_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (intr_capturer_0_avalon_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (intr_capturer_0_avalon_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (intr_capturer_0_avalon_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (intr_capturer_0_avalon_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (intr_capturer_0_avalon_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (intr_capturer_0_avalon_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (intr_capturer_0_avalon_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (intr_capturer_0_avalon_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (intr_capturer_0_avalon_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                                           //              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                                           //                .valid
		.cp_data                 (cmd_mux_002_src_data),                                            //                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                                   //                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                                     //                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                                         //                .channel
		.rf_sink_ready           (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (intr_capturer_0_avalon_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (intr_capturer_0_avalon_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (intr_capturer_0_avalon_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (128),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) intr_capturer_0_avalon_slave_0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                                   //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),             // clk_reset.reset
		.in_data           (intr_capturer_0_avalon_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (intr_capturer_0_avalon_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (intr_capturer_0_avalon_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                           // (terminated)
		.csr_read          (1'b0),                                                            // (terminated)
		.csr_write         (1'b0),                                                            // (terminated)
		.csr_readdata      (),                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated)
		.almost_full_data  (),                                                                // (terminated)
		.almost_empty_data (),                                                                // (terminated)
		.in_empty          (1'b0),                                                            // (terminated)
		.out_empty         (),                                                                // (terminated)
		.in_error          (1'b0),                                                            // (terminated)
		.out_error         (),                                                                // (terminated)
		.in_channel        (1'b0),                                                            // (terminated)
		.out_channel       ()                                                                 // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) intr_capturer_0_avalon_slave_0_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                             //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_startofpacket  (1'b0),                                                      // (terminated)
		.in_endofpacket    (1'b0),                                                      // (terminated)
		.out_startofpacket (),                                                          // (terminated)
		.out_endofpacket   (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (127),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sysid_qsys_control_slave_agent (
		.clk                     (clk_0_clk_clk),                                                //             clk.clk
		.reset                   (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),          //       clk_reset.reset
		.m0_address              (sysid_qsys_control_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (sysid_qsys_control_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (sysid_qsys_control_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (sysid_qsys_control_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (sysid_qsys_control_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (sysid_qsys_control_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (sysid_qsys_control_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (sysid_qsys_control_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (sysid_qsys_control_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (sysid_qsys_control_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (sysid_qsys_control_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (sysid_qsys_control_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (sysid_qsys_control_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (sysid_qsys_control_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (sysid_qsys_control_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (sysid_qsys_control_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (sysid_qsys_control_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (sysid_qsys_control_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (sysid_qsys_control_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (sysid_qsys_control_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (sysid_qsys_control_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (sysid_qsys_control_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (sysid_qsys_control_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (sysid_qsys_control_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (sysid_qsys_control_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (sysid_qsys_control_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (sysid_qsys_control_slave_agent_rdata_fifo_out_ready),          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sysid_qsys_control_slave_agent_rdata_fifo_out_valid),          //                .valid
		.rdata_fifo_sink_data    (sysid_qsys_control_slave_agent_rdata_fifo_out_data),           //                .data
		.rdata_fifo_src_ready    (sysid_qsys_control_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sysid_qsys_control_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (sysid_qsys_control_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                        //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (128),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sysid_qsys_control_slave_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                             //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (sysid_qsys_control_slave_agent_rf_source_data),             //        in.data
		.in_valid          (sysid_qsys_control_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (sysid_qsys_control_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sysid_qsys_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sysid_qsys_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sysid_qsys_control_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sysid_qsys_control_slave_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                       //       clk.clk
		.reset             (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sysid_qsys_control_slave_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (sysid_qsys_control_slave_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                               // (terminated)
		.csr_read          (1'b0),                                                // (terminated)
		.csr_write         (1'b0),                                                // (terminated)
		.csr_readdata      (),                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated)
		.almost_full_data  (),                                                    // (terminated)
		.almost_empty_data (),                                                    // (terminated)
		.in_startofpacket  (1'b0),                                                // (terminated)
		.in_endofpacket    (1'b0),                                                // (terminated)
		.out_startofpacket (),                                                    // (terminated)
		.out_endofpacket   (),                                                    // (terminated)
		.in_empty          (1'b0),                                                // (terminated)
		.out_empty         (),                                                    // (terminated)
		.in_error          (1'b0),                                                // (terminated)
		.out_error         (),                                                    // (terminated)
		.in_channel        (1'b0),                                                // (terminated)
		.out_channel       ()                                                     // (terminated)
	);

	soc_system_mm_interconnect_0_router router (
		.sink_ready         (hps_0_h2f_axi_master_agent_write_cp_ready),                        //      sink.ready
		.sink_valid         (hps_0_h2f_axi_master_agent_write_cp_valid),                        //          .valid
		.sink_data          (hps_0_h2f_axi_master_agent_write_cp_data),                         //          .data
		.sink_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket),                //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_axi_master_agent_write_cp_endofpacket),                  //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                 //       src.ready
		.src_valid          (router_src_valid),                                                 //          .valid
		.src_data           (router_src_data),                                                  //          .data
		.src_channel        (router_src_channel),                                               //          .channel
		.src_startofpacket  (router_src_startofpacket),                                         //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                            //          .endofpacket
	);

	soc_system_mm_interconnect_0_router router_001 (
		.sink_ready         (hps_0_h2f_axi_master_agent_read_cp_ready),                         //      sink.ready
		.sink_valid         (hps_0_h2f_axi_master_agent_read_cp_valid),                         //          .valid
		.sink_data          (hps_0_h2f_axi_master_agent_read_cp_data),                          //          .data
		.sink_startofpacket (hps_0_h2f_axi_master_agent_read_cp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_axi_master_agent_read_cp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                             //       src.ready
		.src_valid          (router_001_src_valid),                                             //          .valid
		.src_data           (router_001_src_data),                                              //          .data
		.src_channel        (router_001_src_channel),                                           //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (fpga_only_master_master_agent_cp_ready),              //      sink.ready
		.sink_valid         (fpga_only_master_master_agent_cp_valid),              //          .valid
		.sink_data          (fpga_only_master_master_agent_cp_data),               //          .data
		.sink_startofpacket (fpga_only_master_master_agent_cp_startofpacket),      //          .startofpacket
		.sink_endofpacket   (fpga_only_master_master_agent_cp_endofpacket),        //          .endofpacket
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                //       src.ready
		.src_valid          (router_002_src_valid),                                //          .valid
		.src_data           (router_002_src_data),                                 //          .data
		.src_channel        (router_002_src_channel),                              //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_003 router_003 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                     //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                     //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                      //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),             //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),               //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                                             //       src.ready
		.src_valid          (router_003_src_valid),                                             //          .valid
		.src_data           (router_003_src_data),                                              //          .data
		.src_channel        (router_003_src_channel),                                           //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_003 router_004 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                      //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                      //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_read_cp_data),                       //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),              //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                                             //       src.ready
		.src_valid          (router_004_src_valid),                                             //          .valid
		.src_data           (router_004_src_data),                                              //          .data
		.src_channel        (router_004_src_channel),                                           //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_005 router_005 (
		.sink_ready         (onchip_memory2_0_s1_agent_rp_ready),                  //      sink.ready
		.sink_valid         (onchip_memory2_0_s1_agent_rp_valid),                  //          .valid
		.sink_data          (onchip_memory2_0_s1_agent_rp_data),                   //          .data
		.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket),          //          .startofpacket
		.sink_endofpacket   (onchip_memory2_0_s1_agent_rp_endofpacket),            //          .endofpacket
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_005_src_ready),                                //       src.ready
		.src_valid          (router_005_src_valid),                                //          .valid
		.src_data           (router_005_src_data),                                 //          .data
		.src_channel        (router_005_src_channel),                              //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_006 router_006 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),          //      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),          //          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),           //          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),    //          .endofpacket
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                                //       src.ready
		.src_valid          (router_006_src_valid),                                //          .valid
		.src_data           (router_006_src_data),                                 //          .data
		.src_channel        (router_006_src_channel),                              //          .channel
		.src_startofpacket  (router_006_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_007 router_007 (
		.sink_ready         (intr_capturer_0_avalon_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (intr_capturer_0_avalon_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (intr_capturer_0_avalon_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                         //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),   // clk_reset.reset
		.src_ready          (router_007_src_ready),                                  //       src.ready
		.src_valid          (router_007_src_valid),                                  //          .valid
		.src_data           (router_007_src_data),                                   //          .data
		.src_channel        (router_007_src_channel),                                //          .channel
		.src_startofpacket  (router_007_src_startofpacket),                          //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                             //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_006 router_008 (
		.sink_ready         (sysid_qsys_control_slave_agent_rp_ready),             //      sink.ready
		.sink_valid         (sysid_qsys_control_slave_agent_rp_valid),             //          .valid
		.sink_data          (sysid_qsys_control_slave_agent_rp_data),              //          .data
		.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (sysid_qsys_control_slave_agent_rp_endofpacket),       //          .endofpacket
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_008_src_ready),                                //       src.ready
		.src_valid          (router_008_src_valid),                                //          .valid
		.src_data           (router_008_src_data),                                 //          .data
		.src_channel        (router_008_src_channel),                              //          .channel
		.src_startofpacket  (router_008_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                           //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (3),
		.PIPELINED                 (0),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.VALID_WIDTH               (5),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.REORDER                   (0)
	) fpga_only_master_master_limiter (
		.clk                    (clk_0_clk_clk),                                         //       clk.clk
		.reset                  (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),   // clk_reset.reset
		.cmd_sink_ready         (router_002_src_ready),                                  //  cmd_sink.ready
		.cmd_sink_valid         (router_002_src_valid),                                  //          .valid
		.cmd_sink_data          (router_002_src_data),                                   //          .data
		.cmd_sink_channel       (router_002_src_channel),                                //          .channel
		.cmd_sink_startofpacket (router_002_src_startofpacket),                          //          .startofpacket
		.cmd_sink_endofpacket   (router_002_src_endofpacket),                            //          .endofpacket
		.cmd_src_ready          (fpga_only_master_master_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (fpga_only_master_master_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (fpga_only_master_master_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (fpga_only_master_master_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (fpga_only_master_master_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_002_src_ready),                                 //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_002_src_valid),                                 //          .valid
		.rsp_sink_channel       (rsp_mux_002_src_channel),                               //          .channel
		.rsp_sink_data          (rsp_mux_002_src_data),                                  //          .data
		.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket),                         //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_002_src_endofpacket),                           //          .endofpacket
		.rsp_src_ready          (fpga_only_master_master_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (fpga_only_master_master_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (fpga_only_master_master_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (fpga_only_master_master_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (fpga_only_master_master_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (fpga_only_master_master_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (fpga_only_master_master_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (3),
		.PIPELINED                 (0),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.VALID_WIDTH               (5),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.REORDER                   (0)
	) hps_0_h2f_lw_axi_master_wr_limiter (
		.clk                    (clk_0_clk_clk),                                                    //       clk.clk
		.reset                  (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_003_src_ready),                                             //  cmd_sink.ready
		.cmd_sink_valid         (router_003_src_valid),                                             //          .valid
		.cmd_sink_data          (router_003_src_data),                                              //          .data
		.cmd_sink_channel       (router_003_src_channel),                                           //          .channel
		.cmd_sink_startofpacket (router_003_src_startofpacket),                                     //          .startofpacket
		.cmd_sink_endofpacket   (router_003_src_endofpacket),                                       //          .endofpacket
		.cmd_src_ready          (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready),                 //   cmd_src.ready
		.cmd_src_data           (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data),                  //          .data
		.cmd_src_channel        (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel),               //          .channel
		.cmd_src_startofpacket  (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket),         //          .startofpacket
		.cmd_src_endofpacket    (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket),           //          .endofpacket
		.rsp_sink_ready         (rsp_mux_003_src_ready),                                            //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_003_src_valid),                                            //          .valid
		.rsp_sink_channel       (rsp_mux_003_src_channel),                                          //          .channel
		.rsp_sink_data          (rsp_mux_003_src_data),                                             //          .data
		.rsp_sink_startofpacket (rsp_mux_003_src_startofpacket),                                    //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_003_src_endofpacket),                                      //          .endofpacket
		.rsp_src_ready          (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready),                 //   rsp_src.ready
		.rsp_src_valid          (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid),                 //          .valid
		.rsp_src_data           (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data),                  //          .data
		.rsp_src_channel        (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel),               //          .channel
		.rsp_src_startofpacket  (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket),         //          .startofpacket
		.rsp_src_endofpacket    (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket),           //          .endofpacket
		.cmd_src_valid          (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data)                 // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (101),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (99),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (3),
		.PIPELINED                 (0),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.VALID_WIDTH               (5),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.REORDER                   (0)
	) hps_0_h2f_lw_axi_master_rd_limiter (
		.clk                    (clk_0_clk_clk),                                                    //       clk.clk
		.reset                  (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_004_src_ready),                                             //  cmd_sink.ready
		.cmd_sink_valid         (router_004_src_valid),                                             //          .valid
		.cmd_sink_data          (router_004_src_data),                                              //          .data
		.cmd_sink_channel       (router_004_src_channel),                                           //          .channel
		.cmd_sink_startofpacket (router_004_src_startofpacket),                                     //          .startofpacket
		.cmd_sink_endofpacket   (router_004_src_endofpacket),                                       //          .endofpacket
		.cmd_src_ready          (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready),                 //   cmd_src.ready
		.cmd_src_data           (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data),                  //          .data
		.cmd_src_channel        (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel),               //          .channel
		.cmd_src_startofpacket  (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket),         //          .startofpacket
		.cmd_src_endofpacket    (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket),           //          .endofpacket
		.rsp_sink_ready         (rsp_mux_004_src_ready),                                            //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_004_src_valid),                                            //          .valid
		.rsp_sink_channel       (rsp_mux_004_src_channel),                                          //          .channel
		.rsp_sink_data          (rsp_mux_004_src_data),                                             //          .data
		.rsp_sink_startofpacket (rsp_mux_004_src_startofpacket),                                    //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_004_src_endofpacket),                                      //          .endofpacket
		.rsp_src_ready          (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready),                 //   rsp_src.ready
		.rsp_src_valid          (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid),                 //          .valid
		.rsp_src_data           (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data),                  //          .data
		.rsp_src_channel        (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel),               //          .channel
		.rsp_src_startofpacket  (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket),         //          .startofpacket
		.rsp_src_endofpacket    (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket),           //          .endofpacket
		.cmd_src_valid          (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data)                 // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_BEGIN_BURST           (133),
		.PKT_BYTE_CNT_H            (117),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_BURST_SIZE_H          (128),
		.PKT_BURST_SIZE_L          (126),
		.PKT_BURST_TYPE_H          (130),
		.PKT_BURST_TYPE_L          (129),
		.PKT_BURSTWRAP_H           (125),
		.PKT_BURSTWRAP_L           (118),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (163),
		.ST_CHANNEL_W              (5),
		.OUT_BYTE_CNT_H            (113),
		.OUT_BURSTWRAP_H           (125),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1")
	) onchip_memory2_0_s1_burst_adapter (
		.clk                   (clk_0_clk_clk),                                           //       cr0.clk
		.reset                 (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),     // cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                       //     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                        //          .data
		.sink0_channel         (cmd_mux_src_channel),                                     //          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                               //          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                 //          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                       //          .ready
		.source0_valid         (onchip_memory2_0_s1_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (onchip_memory2_0_s1_burst_adapter_source0_data),          //          .data
		.source0_channel       (onchip_memory2_0_s1_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (onchip_memory2_0_s1_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (onchip_memory2_0_s1_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1")
	) jtag_uart_avalon_jtag_slave_burst_adapter (
		.clk                   (clk_0_clk_clk),                                                   //       cr0.clk
		.reset                 (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),             // cr0_reset.reset
		.sink0_valid           (cmd_mux_001_src_valid),                                           //     sink0.valid
		.sink0_data            (cmd_mux_001_src_data),                                            //          .data
		.sink0_channel         (cmd_mux_001_src_channel),                                         //          .channel
		.sink0_startofpacket   (cmd_mux_001_src_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket     (cmd_mux_001_src_endofpacket),                                     //          .endofpacket
		.sink0_ready           (cmd_mux_001_src_ready),                                           //          .ready
		.source0_valid         (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (127),
		.ST_CHANNEL_W              (5),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1")
	) sysid_qsys_control_slave_burst_adapter (
		.clk                   (clk_0_clk_clk),                                                //       cr0.clk
		.reset                 (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),          // cr0_reset.reset
		.sink0_valid           (cmd_mux_003_src_valid),                                        //     sink0.valid
		.sink0_data            (cmd_mux_003_src_data),                                         //          .data
		.sink0_channel         (cmd_mux_003_src_channel),                                      //          .channel
		.sink0_startofpacket   (cmd_mux_003_src_startofpacket),                                //          .startofpacket
		.sink0_endofpacket     (cmd_mux_003_src_endofpacket),                                  //          .endofpacket
		.sink0_ready           (cmd_mux_003_src_ready),                                        //          .ready
		.source0_valid         (sysid_qsys_control_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (sysid_qsys_control_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (sysid_qsys_control_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (sysid_qsys_control_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (sysid_qsys_control_slave_burst_adapter_source0_ready)          //          .ready
	);

	soc_system_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                                 //      sink.ready
		.sink_channel       (router_src_channel),                                               //          .channel
		.sink_data          (router_src_data),                                                  //          .data
		.sink_startofpacket (router_src_startofpacket),                                         //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                           //          .endofpacket
		.sink_valid         (router_src_valid),                                                 //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                             //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                             //          .valid
		.src0_data          (cmd_demux_src0_data),                                              //          .data
		.src0_channel       (cmd_demux_src0_channel),                                           //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                     //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux cmd_demux_001 (
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                             //      sink.ready
		.sink_channel       (router_001_src_channel),                                           //          .channel
		.sink_data          (router_001_src_data),                                              //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                     //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                       //          .endofpacket
		.sink_valid         (router_001_src_valid),                                             //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                         //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                         //          .valid
		.src0_data          (cmd_demux_001_src0_data),                                          //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                       //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                                 //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                                    //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
		.clk                (clk_0_clk_clk),                                         //        clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),   //  clk_reset.reset
		.sink_ready         (fpga_only_master_master_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (fpga_only_master_master_limiter_cmd_src_channel),       //           .channel
		.sink_data          (fpga_only_master_master_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (fpga_only_master_master_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (fpga_only_master_master_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (fpga_only_master_master_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_002_src0_ready),                              //       src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                              //           .valid
		.src0_data          (cmd_demux_002_src0_data),                               //           .data
		.src0_channel       (cmd_demux_002_src0_channel),                            //           .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),                      //           .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),                        //           .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                              //       src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                              //           .valid
		.src1_data          (cmd_demux_002_src1_data),                               //           .data
		.src1_channel       (cmd_demux_002_src1_channel),                            //           .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),                      //           .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket),                        //           .endofpacket
		.src2_ready         (cmd_demux_002_src2_ready),                              //       src2.ready
		.src2_valid         (cmd_demux_002_src2_valid),                              //           .valid
		.src2_data          (cmd_demux_002_src2_data),                               //           .data
		.src2_channel       (cmd_demux_002_src2_channel),                            //           .channel
		.src2_startofpacket (cmd_demux_002_src2_startofpacket),                      //           .startofpacket
		.src2_endofpacket   (cmd_demux_002_src2_endofpacket),                        //           .endofpacket
		.src3_ready         (cmd_demux_002_src3_ready),                              //       src3.ready
		.src3_valid         (cmd_demux_002_src3_valid),                              //           .valid
		.src3_data          (cmd_demux_002_src3_data),                               //           .data
		.src3_channel       (cmd_demux_002_src3_channel),                            //           .channel
		.src3_startofpacket (cmd_demux_002_src3_startofpacket),                      //           .startofpacket
		.src3_endofpacket   (cmd_demux_002_src3_endofpacket)                         //           .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux_003 cmd_demux_003 (
		.clk                (clk_0_clk_clk),                                                    //        clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready),                 //       sink.ready
		.sink_channel       (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel),               //           .channel
		.sink_data          (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data),                  //           .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket),         //           .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket),           //           .endofpacket
		.sink_valid         (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data),                // sink_valid.data
		.src0_ready         (cmd_demux_003_src0_ready),                                         //       src0.ready
		.src0_valid         (cmd_demux_003_src0_valid),                                         //           .valid
		.src0_data          (cmd_demux_003_src0_data),                                          //           .data
		.src0_channel       (cmd_demux_003_src0_channel),                                       //           .channel
		.src0_startofpacket (cmd_demux_003_src0_startofpacket),                                 //           .startofpacket
		.src0_endofpacket   (cmd_demux_003_src0_endofpacket),                                   //           .endofpacket
		.src1_ready         (cmd_demux_003_src1_ready),                                         //       src1.ready
		.src1_valid         (cmd_demux_003_src1_valid),                                         //           .valid
		.src1_data          (cmd_demux_003_src1_data),                                          //           .data
		.src1_channel       (cmd_demux_003_src1_channel),                                       //           .channel
		.src1_startofpacket (cmd_demux_003_src1_startofpacket),                                 //           .startofpacket
		.src1_endofpacket   (cmd_demux_003_src1_endofpacket)                                    //           .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux_003 cmd_demux_004 (
		.clk                (clk_0_clk_clk),                                                    //        clk.clk
		.reset              (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready),                 //       sink.ready
		.sink_channel       (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel),               //           .channel
		.sink_data          (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data),                  //           .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket),         //           .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket),           //           .endofpacket
		.sink_valid         (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data),                // sink_valid.data
		.src0_ready         (cmd_demux_004_src0_ready),                                         //       src0.ready
		.src0_valid         (cmd_demux_004_src0_valid),                                         //           .valid
		.src0_data          (cmd_demux_004_src0_data),                                          //           .data
		.src0_channel       (cmd_demux_004_src0_channel),                                       //           .channel
		.src0_startofpacket (cmd_demux_004_src0_startofpacket),                                 //           .startofpacket
		.src0_endofpacket   (cmd_demux_004_src0_endofpacket),                                   //           .endofpacket
		.src1_ready         (cmd_demux_004_src1_ready),                                         //       src1.ready
		.src1_valid         (cmd_demux_004_src1_valid),                                         //           .valid
		.src1_data          (cmd_demux_004_src1_data),                                          //           .data
		.src1_channel       (cmd_demux_004_src1_channel),                                       //           .channel
		.src1_startofpacket (cmd_demux_004_src1_startofpacket),                                 //           .startofpacket
		.src1_endofpacket   (cmd_demux_004_src1_endofpacket)                                    //           .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (clk_0_clk_clk),                                                                      //       clk.clk
		.reset               (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                                  //       src.ready
		.src_valid           (cmd_mux_src_valid),                                                                  //          .valid
		.src_data            (cmd_mux_src_data),                                                                   //          .data
		.src_channel         (cmd_mux_src_channel),                                                                //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                                          //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                            //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                                               //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                                               //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                                             //          .channel
		.sink0_data          (cmd_demux_src0_data),                                                                //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                                       //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                                                         //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                                                           //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                                                           //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                                                         //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                                                            //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),                                                   //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket),                                                     //          .endofpacket
		.sink2_ready         (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready),         //     sink2.ready
		.sink2_valid         (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid),         //          .valid
		.sink2_channel       (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel),       //          .channel
		.sink2_data          (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data),          //          .data
		.sink2_startofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink2_endofpacket   (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket)    //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
		.clk                 (clk_0_clk_clk),                                       //       clk.clk
		.reset               (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                               //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                               //          .valid
		.src_data            (cmd_mux_001_src_data),                                //          .data
		.src_channel         (cmd_mux_001_src_channel),                             //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (cmd_demux_002_src1_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_002_src1_valid),                            //          .valid
		.sink0_channel       (cmd_demux_002_src1_channel),                          //          .channel
		.sink0_data          (cmd_demux_002_src1_data),                             //          .data
		.sink0_startofpacket (cmd_demux_002_src1_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_002_src1_endofpacket),                      //          .endofpacket
		.sink1_ready         (cmd_demux_003_src0_ready),                            //     sink1.ready
		.sink1_valid         (cmd_demux_003_src0_valid),                            //          .valid
		.sink1_channel       (cmd_demux_003_src0_channel),                          //          .channel
		.sink1_data          (cmd_demux_003_src0_data),                             //          .data
		.sink1_startofpacket (cmd_demux_003_src0_startofpacket),                    //          .startofpacket
		.sink1_endofpacket   (cmd_demux_003_src0_endofpacket),                      //          .endofpacket
		.sink2_ready         (cmd_demux_004_src0_ready),                            //     sink2.ready
		.sink2_valid         (cmd_demux_004_src0_valid),                            //          .valid
		.sink2_channel       (cmd_demux_004_src0_channel),                          //          .channel
		.sink2_data          (cmd_demux_004_src0_data),                             //          .data
		.sink2_startofpacket (cmd_demux_004_src0_startofpacket),                    //          .startofpacket
		.sink2_endofpacket   (cmd_demux_004_src0_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
		.clk                 (clk_0_clk_clk),                                       //       clk.clk
		.reset               (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                               //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                               //          .valid
		.src_data            (cmd_mux_002_src_data),                                //          .data
		.src_channel         (cmd_mux_002_src_channel),                             //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (cmd_demux_002_src2_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_002_src2_valid),                            //          .valid
		.sink0_channel       (cmd_demux_002_src2_channel),                          //          .channel
		.sink0_data          (cmd_demux_002_src2_data),                             //          .data
		.sink0_startofpacket (cmd_demux_002_src2_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_002_src2_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_003 (
		.clk                 (clk_0_clk_clk),                                       //       clk.clk
		.reset               (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                               //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                               //          .valid
		.src_data            (cmd_mux_003_src_data),                                //          .data
		.src_channel         (cmd_mux_003_src_channel),                             //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (cmd_demux_002_src3_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_002_src3_valid),                            //          .valid
		.sink0_channel       (cmd_demux_002_src3_channel),                          //          .channel
		.sink0_data          (cmd_demux_002_src3_data),                             //          .data
		.sink0_startofpacket (cmd_demux_002_src3_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_002_src3_endofpacket),                      //          .endofpacket
		.sink1_ready         (cmd_demux_003_src1_ready),                            //     sink1.ready
		.sink1_valid         (cmd_demux_003_src1_valid),                            //          .valid
		.sink1_channel       (cmd_demux_003_src1_channel),                          //          .channel
		.sink1_data          (cmd_demux_003_src1_data),                             //          .data
		.sink1_startofpacket (cmd_demux_003_src1_startofpacket),                    //          .startofpacket
		.sink1_endofpacket   (cmd_demux_003_src1_endofpacket),                      //          .endofpacket
		.sink2_ready         (cmd_demux_004_src1_ready),                            //     sink2.ready
		.sink2_valid         (cmd_demux_004_src1_valid),                            //          .valid
		.sink2_channel       (cmd_demux_004_src1_channel),                          //          .channel
		.sink2_data          (cmd_demux_004_src1_data),                             //          .data
		.sink2_startofpacket (cmd_demux_004_src1_startofpacket),                    //          .startofpacket
		.sink2_endofpacket   (cmd_demux_004_src1_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                                //      sink.ready
		.sink_channel       (router_005_src_channel),                              //          .channel
		.sink_data          (router_005_src_data),                                 //          .data
		.sink_startofpacket (router_005_src_startofpacket),                        //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                          //          .endofpacket
		.sink_valid         (router_005_src_valid),                                //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                //          .valid
		.src0_data          (rsp_demux_src0_data),                                 //          .data
		.src0_channel       (rsp_demux_src0_channel),                              //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                        //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                          //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                //          .valid
		.src1_data          (rsp_demux_src1_data),                                 //          .data
		.src1_channel       (rsp_demux_src1_channel),                              //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                        //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket),                          //          .endofpacket
		.src2_ready         (rsp_demux_src2_ready),                                //      src2.ready
		.src2_valid         (rsp_demux_src2_valid),                                //          .valid
		.src2_data          (rsp_demux_src2_data),                                 //          .data
		.src2_channel       (rsp_demux_src2_channel),                              //          .channel
		.src2_startofpacket (rsp_demux_src2_startofpacket),                        //          .startofpacket
		.src2_endofpacket   (rsp_demux_src2_endofpacket)                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                                //      sink.ready
		.sink_channel       (router_006_src_channel),                              //          .channel
		.sink_data          (router_006_src_data),                                 //          .data
		.sink_startofpacket (router_006_src_startofpacket),                        //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                          //          .endofpacket
		.sink_valid         (router_006_src_valid),                                //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                            //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                            //          .valid
		.src0_data          (rsp_demux_001_src0_data),                             //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                          //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                      //          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                            //      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                            //          .valid
		.src1_data          (rsp_demux_001_src1_data),                             //          .data
		.src1_channel       (rsp_demux_001_src1_channel),                          //          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),                    //          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket),                      //          .endofpacket
		.src2_ready         (rsp_demux_001_src2_ready),                            //      src2.ready
		.src2_valid         (rsp_demux_001_src2_valid),                            //          .valid
		.src2_data          (rsp_demux_001_src2_data),                             //          .data
		.src2_channel       (rsp_demux_001_src2_channel),                          //          .channel
		.src2_startofpacket (rsp_demux_001_src2_startofpacket),                    //          .startofpacket
		.src2_endofpacket   (rsp_demux_001_src2_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                                //      sink.ready
		.sink_channel       (router_007_src_channel),                              //          .channel
		.sink_data          (router_007_src_data),                                 //          .data
		.sink_startofpacket (router_007_src_startofpacket),                        //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                          //          .endofpacket
		.sink_valid         (router_007_src_valid),                                //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                            //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                            //          .valid
		.src0_data          (rsp_demux_002_src0_data),                             //          .data
		.src0_channel       (rsp_demux_002_src0_channel),                          //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_003 (
		.clk                (clk_0_clk_clk),                                       //       clk.clk
		.reset              (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_008_src_ready),                                //      sink.ready
		.sink_channel       (router_008_src_channel),                              //          .channel
		.sink_data          (router_008_src_data),                                 //          .data
		.sink_startofpacket (router_008_src_startofpacket),                        //          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                          //          .endofpacket
		.sink_valid         (router_008_src_valid),                                //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                            //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                            //          .valid
		.src0_data          (rsp_demux_003_src0_data),                             //          .data
		.src0_channel       (rsp_demux_003_src0_channel),                          //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),                      //          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),                            //      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),                            //          .valid
		.src1_data          (rsp_demux_003_src1_data),                             //          .data
		.src1_channel       (rsp_demux_003_src1_channel),                          //          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),                    //          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket),                      //          .endofpacket
		.src2_ready         (rsp_demux_003_src2_ready),                            //      src2.ready
		.src2_valid         (rsp_demux_003_src2_valid),                            //          .valid
		.src2_data          (rsp_demux_003_src2_data),                             //          .data
		.src2_channel       (rsp_demux_003_src2_channel),                          //          .channel
		.src2_startofpacket (rsp_demux_003_src2_startofpacket),                    //          .startofpacket
		.src2_endofpacket   (rsp_demux_003_src2_endofpacket)                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                //          .valid
		.src_data            (rsp_mux_src_data),                                                 //          .data
		.src_channel         (rsp_mux_src_channel),                                              //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                          //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                             //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                             //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                           //          .channel
		.sink0_data          (rsp_demux_src0_data),                                              //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux rsp_mux_001 (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                            //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                            //          .valid
		.src_data            (rsp_mux_001_src_data),                                             //          .data
		.src_channel         (rsp_mux_001_src_channel),                                          //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                      //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                                             //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                                             //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                                           //          .channel
		.sink0_data          (rsp_demux_src1_data),                                              //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
		.clk                 (clk_0_clk_clk),                                                                      //       clk.clk
		.reset               (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                                                              //       src.ready
		.src_valid           (rsp_mux_002_src_valid),                                                              //          .valid
		.src_data            (rsp_mux_002_src_data),                                                               //          .data
		.src_channel         (rsp_mux_002_src_channel),                                                            //          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                                                        //          .endofpacket
		.sink0_ready         (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready),         //     sink0.ready
		.sink0_valid         (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid),         //          .valid
		.sink0_channel       (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel),       //          .channel
		.sink0_data          (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data),          //          .data
		.sink0_startofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket   (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                                                           //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                                                           //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                                                         //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                                                            //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                                                   //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                                                     //          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                                                           //     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                                                           //          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                                                         //          .channel
		.sink2_data          (rsp_demux_002_src0_data),                                                            //          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                                                   //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                                                     //          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                                                           //     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                                                           //          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                                                         //          .channel
		.sink3_data          (rsp_demux_003_src0_data),                                                            //          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                                                   //          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket)                                                      //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux_003 rsp_mux_003 (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_003_src_ready),                                            //       src.ready
		.src_valid           (rsp_mux_003_src_valid),                                            //          .valid
		.src_data            (rsp_mux_003_src_data),                                             //          .data
		.src_channel         (rsp_mux_003_src_channel),                                          //          .channel
		.src_startofpacket   (rsp_mux_003_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket     (rsp_mux_003_src_endofpacket),                                      //          .endofpacket
		.sink0_ready         (rsp_demux_001_src1_ready),                                         //     sink0.ready
		.sink0_valid         (rsp_demux_001_src1_valid),                                         //          .valid
		.sink0_channel       (rsp_demux_001_src1_channel),                                       //          .channel
		.sink0_data          (rsp_demux_001_src1_data),                                          //          .data
		.sink0_startofpacket (rsp_demux_001_src1_startofpacket),                                 //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src1_endofpacket),                                   //          .endofpacket
		.sink1_ready         (rsp_demux_003_src1_ready),                                         //     sink1.ready
		.sink1_valid         (rsp_demux_003_src1_valid),                                         //          .valid
		.sink1_channel       (rsp_demux_003_src1_channel),                                       //          .channel
		.sink1_data          (rsp_demux_003_src1_data),                                          //          .data
		.sink1_startofpacket (rsp_demux_003_src1_startofpacket),                                 //          .startofpacket
		.sink1_endofpacket   (rsp_demux_003_src1_endofpacket)                                    //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux_003 rsp_mux_004 (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_004_src_ready),                                            //       src.ready
		.src_valid           (rsp_mux_004_src_valid),                                            //          .valid
		.src_data            (rsp_mux_004_src_data),                                             //          .data
		.src_channel         (rsp_mux_004_src_channel),                                          //          .channel
		.src_startofpacket   (rsp_mux_004_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket     (rsp_mux_004_src_endofpacket),                                      //          .endofpacket
		.sink0_ready         (rsp_demux_001_src2_ready),                                         //     sink0.ready
		.sink0_valid         (rsp_demux_001_src2_valid),                                         //          .valid
		.sink0_channel       (rsp_demux_001_src2_channel),                                       //          .channel
		.sink0_data          (rsp_demux_001_src2_data),                                          //          .data
		.sink0_startofpacket (rsp_demux_001_src2_startofpacket),                                 //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src2_endofpacket),                                   //          .endofpacket
		.sink1_ready         (rsp_demux_003_src2_ready),                                         //     sink1.ready
		.sink1_valid         (rsp_demux_003_src2_valid),                                         //          .valid
		.sink1_channel       (rsp_demux_003_src2_channel),                                       //          .channel
		.sink1_data          (rsp_demux_003_src2_data),                                          //          .data
		.sink1_startofpacket (rsp_demux_003_src2_startofpacket),                                 //          .startofpacket
		.sink1_endofpacket   (rsp_demux_003_src2_endofpacket)                                    //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (81),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (89),
		.IN_PKT_BURSTWRAP_L            (82),
		.IN_PKT_BURST_SIZE_H           (92),
		.IN_PKT_BURST_SIZE_L           (90),
		.IN_PKT_RESPONSE_STATUS_H      (123),
		.IN_PKT_RESPONSE_STATUS_L      (122),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (94),
		.IN_PKT_BURST_TYPE_L           (93),
		.IN_PKT_ORI_BURST_SIZE_L       (124),
		.IN_PKT_ORI_BURST_SIZE_H       (126),
		.IN_ST_DATA_W                  (127),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (117),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (128),
		.OUT_PKT_BURST_SIZE_L          (126),
		.OUT_PKT_RESPONSE_STATUS_H     (159),
		.OUT_PKT_RESPONSE_STATUS_L     (158),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (130),
		.OUT_PKT_BURST_TYPE_L          (129),
		.OUT_PKT_ORI_BURST_SIZE_L      (160),
		.OUT_PKT_ORI_BURST_SIZE_H      (162),
		.OUT_ST_DATA_W                 (163),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1)
	) fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter (
		.clk                  (clk_0_clk_clk),                                                                      //       clk.clk
		.reset                (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.in_valid             (cmd_demux_002_src0_valid),                                                           //      sink.valid
		.in_channel           (cmd_demux_002_src0_channel),                                                         //          .channel
		.in_startofpacket     (cmd_demux_002_src0_startofpacket),                                                   //          .startofpacket
		.in_endofpacket       (cmd_demux_002_src0_endofpacket),                                                     //          .endofpacket
		.in_ready             (cmd_demux_002_src0_ready),                                                           //          .ready
		.in_data              (cmd_demux_002_src0_data),                                                            //          .data
		.out_endofpacket      (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data),          //          .data
		.out_channel          (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (117),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (125),
		.IN_PKT_BURSTWRAP_L            (118),
		.IN_PKT_BURST_SIZE_H           (128),
		.IN_PKT_BURST_SIZE_L           (126),
		.IN_PKT_RESPONSE_STATUS_H      (159),
		.IN_PKT_RESPONSE_STATUS_L      (158),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (130),
		.IN_PKT_BURST_TYPE_L           (129),
		.IN_PKT_ORI_BURST_SIZE_L       (160),
		.IN_PKT_ORI_BURST_SIZE_H       (162),
		.IN_ST_DATA_W                  (163),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (81),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (92),
		.OUT_PKT_BURST_SIZE_L          (90),
		.OUT_PKT_RESPONSE_STATUS_H     (123),
		.OUT_PKT_RESPONSE_STATUS_L     (122),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (94),
		.OUT_PKT_BURST_TYPE_L          (93),
		.OUT_PKT_ORI_BURST_SIZE_L      (124),
		.OUT_PKT_ORI_BURST_SIZE_H      (126),
		.OUT_ST_DATA_W                 (127),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1)
	) onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter (
		.clk                  (clk_0_clk_clk),                                                                      //       clk.clk
		.reset                (onchip_memory2_0_reset1_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.in_valid             (rsp_demux_src2_valid),                                                               //      sink.valid
		.in_channel           (rsp_demux_src2_channel),                                                             //          .channel
		.in_startofpacket     (rsp_demux_src2_startofpacket),                                                       //          .startofpacket
		.in_endofpacket       (rsp_demux_src2_endofpacket),                                                         //          .endofpacket
		.in_ready             (rsp_demux_src2_ready),                                                               //          .ready
		.in_data              (rsp_demux_src2_data),                                                                //          .data
		.out_endofpacket      (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data),          //          .data
		.out_channel          (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated)
	);

endmodule
